Paper
27 March 2007 Pitch doubling through dual-patterning lithography challenges in integration and litho budgets
Mircea Dusa, John Quaedackers, Olaf F. A. Larsen, Jeroen Meessen, Eddy van der Heijden, Gerald Dicker, Onno Wismans, Paul de Haas, Koen van Ingen Schenau, Jo Finders, Bert Vleeming, Geert Storms, Patrick Jaenen, Shaunee Cheng, Mireille Maenhoudt
Author Affiliations +
Abstract
We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 1.2NA lithography system. Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process. Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step. This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations. Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM. They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions. We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance. For a single line and 1.35NA system, the model predicted 3.1nm variance with mask CDU and etch bias being the major contributors. We achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA system, which equals 0.20k1. Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s). After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 2.5nm (3s). Best overlay results equaled scanner SMO capability of ~7nm (mean+3s).
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mircea Dusa, John Quaedackers, Olaf F. A. Larsen, Jeroen Meessen, Eddy van der Heijden, Gerald Dicker, Onno Wismans, Paul de Haas, Koen van Ingen Schenau, Jo Finders, Bert Vleeming, Geert Storms, Patrick Jaenen, Shaunee Cheng, and Mireille Maenhoudt "Pitch doubling through dual-patterning lithography challenges in integration and litho budgets", Proc. SPIE 6520, Optical Microlithography XX, 65200G (27 March 2007); https://doi.org/10.1117/12.714278
Lens.org Logo
CITATIONS
Cited by 82 scholarly publications and 19 patents.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Etching

Semiconducting wafers

Double patterning technology

Optical lithography

Overlay metrology

Critical dimension metrology

Lithography

Back to Top