Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

Antonio J. Acosta; José M. Mora; Javier Castro; Pilar Parra

doi:10.1117/12.724162

23 May 2007 Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

Antonio J. Acosta, José M. Mora, Javier Castro, Pilar Parra

Proceedings Volume 6590, VLSI Circuits and Systems III; 659007 (2007) https://doi.org/10.1117/12.724162
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain

Abstract

The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire, as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also received much attention, because of the low power requirements of modern integrated systems. In the same way, the buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption, but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible impact on average power consumption.

Citation Download Citation

Antonio J. Acosta, José M. Mora, Javier Castro, and Pilar Parra "Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits", Proc. SPIE 6590, VLSI Circuits and Systems III, 659007 (23 May 2007); https://doi.org/10.1117/12.724162

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
8 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Picosecond phenomena

Switching

Very large scale integration

Digital electronics

Power supplies

Transistors

Logic

Show All Keywords

Keywords/Phrases

Search In:

Publication Years