A routing clean-up methodology for improvement of defect and lithography related yield

Jacques Herry; Reinhard März; Hanno Melzner; Kai Peter; Olivier Rizzo

doi:10.1117/12.770292

4 March 2008 A routing clean-up methodology for improvement of defect and lithography related yield

Jacques Herry, Reinhard März, Hanno Melzner, Kai Peter, Olivier Rizzo

Author Affiliations +

Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 69250J (2008) https://doi.org/10.1117/12.770292
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

Particle induced defects are still one of the major sources of yield loss in semiconductor manufacturing. In addition, optical distortion of shapes cannot be ignored in modern technologies and requires increasing design effort in order to avoid yield loss and minimize manufacturing costs. Although suppliers of automated routing tools are increasingly addressing these issues, we still see significant improvement potential even in layouts produced by routers attributed as DfM aware. We propose a post-routing clean-up step to address both defect and lithography related yield loss in the routing layers. In contrast to a "find and fix" approach, this methodology creates lithography friendly layout "by construction", based on the general concept of shape simplification and standardization.

Citation Download Citation

Jacques Herry, Reinhard März, Hanno Melzner, Kai Peter, and Olivier Rizzo "A routing clean-up methodology for improvement of defect and lithography related yield", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250J (4 March 2008); https://doi.org/10.1117/12.770292

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