Modeling of vertical transistor with electrically variable junctions in ISE TCAD

A. E. Rogozhin; I. A. Khorin; D. G. Drozdov; A. G. Vasiliev

doi:10.1117/12.802536

29 April 2008 Modeling of vertical transistor with electrically variable junctions in ISE TCAD

A. E. Rogozhin, I. A. Khorin, D. G. Drozdov, A. G. Vasiliev

Proceedings Volume 7025, Micro- and Nanoelectronics 2007; 70251O (2008) https://doi.org/10.1117/12.802536
Event: Micro- and Nanoelectronics 2007, 2007, Zvenigorod, Russian Federation

Abstract

In this work we present the results of simulation of vertical MOS transistor with electrically variable shallow junctions in ISE TCAD. Transistor with fully silicided gate electrodes, two heavy doped delta-layers in the channel region and ZrO₂ as a gate dielectric has been simulated. The simulation used different carrier transport and mobility models. High values of on-state current have been obtained during the simulation process (~1.2 mA/μm). Different voltage regimes for middle and side gates have been assumed. Values of direct leakage current from drain to source got from simulation are relatively low and amount to approximately 0.02 μA/μm². These values show that use of electrically variable junctions and doped delta-layers really suppresses short-channel effects and reduces direct leakage current from drain to source. Technology of electrically variable junctions allows to employ vertical transistor into high-performance logic applications.

Citation Download Citation

A. E. Rogozhin, I. A. Khorin, D. G. Drozdov, and A. G. Vasiliev "Modeling of vertical transistor with electrically variable junctions in ISE TCAD", Proc. SPIE 7025, Micro- and Nanoelectronics 2007, 70251O (29 April 2008); https://doi.org/10.1117/12.802536

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