Increased uniformity control in a 45nm polysilicon gate etch process

Blake Parkinson; Dan Prager; Merritt Funk; Radha Sundararajan; Asao Yamashita; Kenneth Bandy; Eric Meyette

doi:10.1117/12.816095

23 March 2009 Increased uniformity control in a 45nm polysilicon gate etch process

Blake Parkinson, Dan Prager, Merritt Funk, Radha Sundararajan, Asao Yamashita, Kenneth Bandy, Eric Meyette

Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 72721J (2009) https://doi.org/10.1117/12.816095
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist trim, and gate etch in order to achieve the demanding CD control tolerances. Currently, APC is used in the lithography and etch processes for within wafer (WiW) and wafer-to-wafer (W2W) CD control. APC can make improvements in process results, but there is still variation that needs to be further reduced. Analysis of the current lithography edge CD showed that the variation trend transferred to the post-etch edge CD measurement. Additionally, the etch process created variation in the edge CD independently of the lithography process. It can be challenging to compensate for the variations in the etch process and such compensations degrade through pitch OPC. Multivariable control of the etch process can reduce the need for compensations and, consequently, through pitch variation. A DOE was designed and run using the production etch process as a center reference for the creation of a WiW etch control model. This control model was then tested with a MATLAB based simulation program that simulates the etch production process sequence and the ability to target the edge CD. This demonstration shows that through rigorous methodology a multivariate model can be created for targeting both center CD (W2W) and edge CD (WiW) control, providing an opportunity at etch to reduce compensation for the etch variations at litho, and to provide the capability at etch to compensate for both litho and etch uniformity changes by wafer.

Citation Download Citation

Blake Parkinson, Dan Prager, Merritt Funk, Radha Sundararajan, Asao Yamashita, Kenneth Bandy, and Eric Meyette "Increased uniformity control in a 45nm polysilicon gate etch process", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72721J (23 March 2009); https://doi.org/10.1117/12.816095

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KEYWORDS

Critical dimension metrology

Etching

Semiconducting wafers

Lithography

Process control

Diffractive optical elements

Data centers

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