Improvements in process performance for immersion technology high volume manufacturing

K. Nafus; T. Shimoaoki; M. Enomoto; H. Shite; T. Otsuka; H. Kosugi; T. Shibata; J. Mallmann; R. Maas; C. Verspaget; E. van der Heijden; E. van Setten; J. Finders; S. Wang; N. Boudou; C. Zoldesi

doi:10.1117/12.813485

1 April 2009 Improvements in process performance for immersion technology high volume manufacturing

K. Nafus, T. Shimoaoki, M. Enomoto, H. Shite, T. Otsuka, H. Kosugi, T. Shibata, J. Mallmann, R. Maas, C. Verspaget, E. van der Heijden, E. van Setten, J. Finders, S. Wang, N. Boudou, C. Zoldesi

Author Affiliations +

Proceedings Volume 7273, Advances in Resist Materials and Processing Technology XXVI; 727338 (2009) https://doi.org/10.1117/12.813485
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

Through collaborative efforts ASML and TEL are continuously improving the process performance for the LITHIUS Pro -i/ TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML have investigated the CDU and defectivity performance for the 45nm node with high through put processing. CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from the multi-module processing on the LITHIUS Pro -i, using a topcoat resist process. For increased productivity, a new bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface. However, with the necessity of double patterning for at least the next technology node, more stringent requirements are necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity. In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized. Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated. Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.

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K. Nafus, T. Shimoaoki, M. Enomoto, H. Shite, T. Otsuka, H. Kosugi, T. Shibata, J. Mallmann, R. Maas, C. Verspaget, E. van der Heijden, E. van Setten, J. Finders, S. Wang, N. Boudou, and C. Zoldesi "Improvements in process performance for immersion technology high volume manufacturing", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 727338 (1 April 2009); https://doi.org/10.1117/12.813485

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