Topcoat-less resist process development for contact layer of 40nm node logic devices

Masafumi Fujita; Takayuki Uchiyama; Tetsunari Furusho; Takahisa Otsuka; Katsuhiro Tsuchiya

doi:10.1117/12.846270

30 March 2010 Top coat less resist process development for contact layer of 40nm node logic devices

Masafumi Fujita, Takayuki Uchiyama, Tetsunari Furusho, Takahisa Otsuka, Katsuhiro Tsuchiya

Proceedings Volume 7639, Advances in Resist Materials and Processing Technology XXVII; 763923 (2010) https://doi.org/10.1117/12.846270
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

ArF immersion lithography has been introduced in mass production of 55nm node devices and beyond as the post ArF dry lithography. Due to the existence of water between the resist film and lens, we have many concerns such as leaching of PAG and quencher from resist film into immersion water, resist film swelling by water, keeping water in the immersion hood to avoid water droplets coming in contact with the wafer, and so on. We have applied to the ArF dry resist process an immersion topcoat (TC) process in order to ensure the hydrophobic property as well as one for protecting the surface. We investigate the TC-less resist process with an aim to improve CoO, the yield and productivity in mass production of immersion lithography. In this paper, we will report TC-less resist process development for the contact layer of 40nm node logic devices. It is important to control the resist surface condition to reduce pattern defects, in particular in the case of the contact layer. We evaluated defectivity and lithography performance of TC-less resist with changing hydrophobicity before and after development. Hydrophobicity of TC-less resist was controlled by changing additives with TC functions introduced into conventional ArF dry resist. However, the hydrophobicity control was not sufficient to reduce the number of Blob defects compared with the TC process. Therefore, we introduced Advanced Defect Reduction (ADR) rinse, which was a new developer rinse technique that is effective against hydrophobic surfaces. We have realized Blob defect reduction by hydrophobicity control and ADR rinse. Furthermore, we will report device performance, yield, and immersion defect data at 40nm node logic devices with TC-less resist process.

Citation Download Citation

Masafumi Fujita, Takayuki Uchiyama, Tetsunari Furusho, Takahisa Otsuka, and Katsuhiro Tsuchiya "Top coat less resist process development for contact layer of 40nm node logic devices", Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 763923 (30 March 2010); https://doi.org/10.1117/12.846270

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