Implementation of 2-D DCT based on FPGA

Bao-Zeng Guo; Li Niu; Zhi-Ming Liu

doi:10.1117/12.867104

19 August 2010 Implementation of 2-D DCT based on FPGA

Bao-Zeng Guo, Li Niu, Zhi-Ming Liu

Proceedings Volume 7820, International Conference on Image Processing and Pattern Recognition in Industrial Engineering; 782004 (2010) https://doi.org/10.1117/12.867104
Event: International Conference on Image Processing and Pattern Recognition in Industrial Engineering, 2010, Xi'an, China

Abstract

Discrete Cosine Transform (DCT) plays an important role in the image and video compression, and it has been widely used in JPEG, MPEG, H.26x. DCT being implemented by hardware is crucial to improve the speed of image compression. This paper presents a method that 2-D DCT is implemented by FPGA, which is based on the algorithm of row-column decomposition, and the parallel structure is used to achieve high throughput. The design is achieved by top-down design methodology and described with Verilog HDL in RTL level. The hardware of 2-D DCT is implemented by the FPGA EP2C35F672C8 made by ALTERA. The experiment results show that the delay time is as low as 15 ns, and the clock frequency as high as 138.35 MHz, which can satisfy the requirements of the real-time video image compression.

Citation Download Citation

Bao-Zeng Guo, Li Niu, and Zhi-Ming Liu "Implementation of 2-D DCT based on FPGA", Proc. SPIE 7820, International Conference on Image Processing and Pattern Recognition in Industrial Engineering, 782004 (19 August 2010); https://doi.org/10.1117/12.867104

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