Paper
7 April 2011 EUV lithography at chipmakers has started: performance validation of ASML's NXE:3100
Christian Wagner, Jose Bacelar, Noreen Harned, Erik Loopstra, Stef Hendriks, Ivo de Jong, Peter Kuerz, Leon Levasier, Mark van de Kerkhof, Martin Lowisch, Hans Meiling, David Ockwell, Rudy Peeters, Eelco van Setten, Judon Stoeldraijer, Stuart Young, John Zimmerman, Ron Kool
Author Affiliations +
Abstract
With the 1st NXE:3100 being operational at a Semiconductor Manufacturer and a 2nd system being shipped at the time of writing this paper, we enter the next phase in the implementation of EUV Lithography. Since 2006 process and early device verification has been done using the two Alpha Demo Tools (ADT's) located at IMEC in Leuven, Belgium and at the CSNE in Albany, New York, USA. Now process integration has started at actual Chipmakers sites. This is a major step for the development and implementation of EUVL. The focus is now on the integration of exposure tools into a manufacturing flow, preparing high volume manufacturing expected to start in 2013. While last year's NXE:3100 paper focused on module performance including optics, leveling and stages, this years update will, in detail, assess imaging, overlay and productivity performance. Based on data obtained during the integration phase of the NXE:3100 we will assess the readiness of the system for process integration at 27nm hp and below. Imaging performance with both conventional and off-axis illumination will be evaluated. Although single exposure processes offer some relief, overlay requirements continue to be challenging for exposure tools. We will share the status of the overlay performance of the NXE:3100. Source power is a key element in reaching the productivity of the NXE:3100 - its status will be discussed as well. Looking forward to high volume manufacturing with EUV we will update on the design status of the NXE:3300B being introduced in 2012 with a productivity target of 125wph. Featuring a 0.33NA lens and off-axis illumination at full transmission, a half pitch resolution from 22nm to 16nm can be supported. In order to ensure a solid volume ramp-up the NXE:3300B will be built on as many building blocks from the NXE:3100 as possible making optimum use of the NXE platform concept.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christian Wagner, Jose Bacelar, Noreen Harned, Erik Loopstra, Stef Hendriks, Ivo de Jong, Peter Kuerz, Leon Levasier, Mark van de Kerkhof, Martin Lowisch, Hans Meiling, David Ockwell, Rudy Peeters, Eelco van Setten, Judon Stoeldraijer, Stuart Young, John Zimmerman, and Ron Kool "EUV lithography at chipmakers has started: performance validation of ASML's NXE:3100", Proc. SPIE 7969, Extreme Ultraviolet (EUV) Lithography II, 79691F (7 April 2011); https://doi.org/10.1117/12.878603
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Cited by 29 scholarly publications.
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KEYWORDS
Semiconducting wafers

Reticles

Extreme ultraviolet lithography

Overlay metrology

Optical proximity correction

Contamination

Extreme ultraviolet

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