Scaling trends of single-photon avalanche diode arrays in nanometer CMOS technology

Justin A. Richardson; Eric A. G. Webster; Lindsay A. Grant; Robert K. Henderson

doi:10.1117/12.884097

12 May 2011 Scaling trends of single-photon avalanche diode arrays in nanometer CMOS technology

Justin A. Richardson, Eric A. G. Webster, Lindsay A. Grant, Robert K. Henderson

Proceedings Volume 8033, Advanced Photon Counting Techniques V; 80330B (2011) https://doi.org/10.1117/12.884097
Event: SPIE Defense, Security, and Sensing, 2011, Orlando, Florida, United States

Abstract

A family of scaleable single photon avalanche diode (SPAD) structures in 130nm and 90nm CMOS is presented. Performance trends such as dark count rate (DCR), jitter and breakdown voltage are studied versus active diameter for devices ranging from 32μm down to 2μm. To address pixel pitch we introduce a shared buried n-well approach allowing compact arrays containing both NMOS-transistor readout circuitry and SPAD devices. A pixel pitch of 5μm has been achieved in 90nm CMOS technology, offering the potential for future megapixel single photon image sensors.

Citation Download Citation

Justin A. Richardson, Eric A. G. Webster, Lindsay A. Grant, and Robert K. Henderson "Scaling trends of single-photon avalanche diode arrays in nanometer CMOS technology", Proc. SPIE 8033, Advanced Photon Counting Techniques V, 80330B (12 May 2011); https://doi.org/10.1117/12.884097

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