See-through-silicon inspection application studies based on traditional silicon imager

Wei Zhou; Darcy Hart; Noah Bock; Rolf Shervey

doi:10.1117/12.892576

20 September 2011 See-through-silicon inspection application studies based on traditional silicon imager

Wei Zhou, Darcy Hart, Noah Bock, Rolf Shervey

Proceedings Volume 8105, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors V; 81050H (2011) https://doi.org/10.1117/12.892576
Event: SPIE NanoScience + Engineering, 2011, San Diego, California, United States

Abstract

With semiconductor development processes hitting harder and harder on Moore's law to continuously scale down, high density advanced packaging technologies become a promising alternate route to improve transistor density. Chip integration IO/cm² density jumps quickly by orders from 2D packaging of 10² to wire bonded chip stack of 10³, to TSV of 104~105 and to advanced 3D integration of 10⁵ to 10⁶. Starting with wire bonding and now prevailing with TSV, more and more silicon layers are stacked up in 3D dimension to improve system density. A typical stacked wafer sample has two wafers glued together with patterned area sandwiched in between. Outer surfaces can be polished or unpolished bare silicon surface, or patterned surface.

Citation Download Citation

Wei Zhou, Darcy Hart, Noah Bock, and Rolf Shervey "See-through-silicon inspection application studies based on traditional silicon imager", Proc. SPIE 8105, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors V, 81050H (20 September 2011); https://doi.org/10.1117/12.892576

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