This PDF file contains the front matter associated with SPIE Proceedings Volume 8685, including the Title Page, Copyright Information, Table of Contents, Introduction and Conference Committee listing.

Patterning methods for sub-10nm half pitch are discussed. Four patterning methods are selected due to discussing their feasibility: immersion lithography with self-aligned octuplet patterning (Imm-SAOP), EUVL with self-aligned double patterning (EUV-SADP), EUVL with litho-etch-litho-etch (EUV-LELE) and EUVL with directed self-assembly (EUV-DSA). There are two significant issues in lithography process and etch process: iso-dense bias and CD variation. Relaxation of design rule except for memory cell makes iso-dense bias issue not critical. However, CD variation influences directly device characterization. CD variation formula are established for the four patterning method described above. Assuming the challenging spec for each unit process, CD variation is estimated for the four patterning methods using the formula. Although EUV-SADP and EUV-DSA are candidates for sub-10nm patterning technology, Imm-SAOP and EUV-LELE are out of spec required from device characteristics.

Various forms of Optical Proximity Correction (OPC) have been employed for over twenty years to address local lithographic printing effects. As lithography modeling capabilities have improved, so too have the sophistication and complexity of OPC solutions. In the same time frame, there have been advances in etch modeling capabilities, but the complexity of the correction schemes used to address etch effects have lagged a few years behind lithographic OPC correction. In this paper we examine some of the challenges faced in etch modeling and correction. We describe some of the etch correction tools and techniques used in current mask tape out flows. Finally, we use the last few years of advances in OPC correction to predict what form etch correction will take going forward, both in EUV flows, and in traditional non-EUV OPC flows in the 10nm node and beyond.

Line Edge Roughness (LER) is of great concern in all new generation lithographies and plays a significant role in the evaluation of the future materials and processes. However, LER studies are not limited to lithography. Metrology, device physics and recently plasma etching technology investigate complementary aspects of LER in their own terms and using their own methodologies. This means that LER is actually a multifaceted issue and its understanding and control demands an effective cooperation and integration of all the involved areas and approaches. To this end, in this paper we discuss first the importance of an advanced LER characterization methodology to bring together the lithographic approach to LER and its impact on device performance. Then, we introduce a background modeling for the pattern transfer effects on LER during plasma etching which reveals the critical role of resist LER on the quality of the printed to the substrate line after plasma etching in harmony with experimental results. The overall conclusion seems to be that the advanced characterization of the whole aspects of LER strengthens the links between lithographic LER, its transfer to the substrate after plasma etching and its effects on device operation.

Smoothing effects of post-litho plasma treatment on 22nm lines and spaces are evaluated for two types of EUV photo resists. This paper shows that different plasma conditions will be required to obtain a similar or better roughness reduction as previously reported for 30 nm lines. A first screening indicates a reduction in LWR of about 10% by using a H₂ plasma smoothing process. This smoothing is mainly triggered by the synergy of H₂ radical and ionic species during plasma treatment. Moreover the smoothing process is highly dependent on the polymer chemistry.

As 14nm node devices begin to permeate into the semiconductor industry, it is becoming increasingly evident that continued pitch scaling is getting more complex throughout the FEOL, MOL and BEOL. The adoption of patterning schemes and pitch splitting techniques such as double exposure/double etch and sidewall image transfer (SIT) are already underway to extend 193nm immersion lithography and enable 3D FinFET / Trigate devices. In addition, BEOL scaling of damascene copper is facing its own challenges, between the patterning and integration of porous ULK materials and the issue of increased resistivity emanating from grain boundary and surface scattering. As such, this paper will present work on novel etch methods envisioned to enable the successful extension of patterning and device integration for the 10nm node and beyond. Work related to the exploration of novel feedgas chemistries to extend etch performance for SiN spacer and oxide etch applications will be reviewed in detail. Specifically, the realization of a silicon nitride etch process which no longer depends on an oxidation mechanism, but rather a polymerization based etch mechanism will be shown. The process exhibits high selectivity to SiO₂, Si and photoresist and results in reduced SOI loss while simultaneously maintaining all SiN on the gate sidewall and significantly reducing SiN footing. In addition, the feasibility of novel patterning methods such as the introduction of subtractive etching of copper will be reviewed in detail. Subtractive etching of Cu has the potential to overcome current interconnect integration difficulties by enabling blanket Cu film deposition with large grains, and by minimizing plasma damage during ULK etch, respectively. Successful patterning of copper at 25-50nm critical dimension (CD) with smaller than 100nm in pitch is demonstrated using a novel high density plasma based dry etch process.

With the constant decrease of semiconductor device dimensions, gate Line Edge Roughness (LER) becomes one of the most important sources of device variability and needs to be controlled well below 2 nm for the future technological nodes of the semiconductor roadmap. Gate LER originates from photoresist (PR) LER that is partially transferred into the gate during the plasma etch process. A plasma treatment is typically used to reduce the PR LER before the transfer. We have shown that an HBr plasma treatment reduces the LER by about 30% whereas an HBr/O₂ plasma treatment followed by a bake at 150°C can reduce the LER further, by about 50%. The LER control at the nanometer scale also requires accurate measurements. We have developed a technique for LER measurement based upon Atomic Force Microscopy (AFM). In this technique, the sample is tilted at about 45° and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The small radius of curvature of the tip together with the low noise level of a laboratory AFM result in high resolution images. Half profiles and LER values on all the height of the sidewalls are extracted from the 3D images using a procedure that we developed. The AFM technique is applied to the study of a full pattern transfer into a simplified gate stack starting from untreated PR, PR treated by a conventional HBr plasma, and PR treated by an HBr/O₂ plasma followed by a bake at 150°C. It is found that plasma etching reduces the LER at each etching step. The reduction is much more important when starting from untreated PR which has the highest initial LER. However, the final LER in the Si layer remains significantly smaller when starting with cured PR, especially with PR cured by an HBr/O₂ plasma treatment followed by a bake at 150°C.

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

In the past a few years, there has been a trend that non-planar field effect transistors (FETs) replace planar counterparts in semiconductor industry. One of critical and challenging processes to fabricate this non-planar device in bulk Si wafers is forming the array of tall Si fins with tight pitch that is used for gate channel as well as source and drain. Fin formation process typically involves deep Si etch using hard mask formed by double patterning technique (DPT). Traditional Si etch tends to results in intra-cell depth loading due to pitch walking and necking profile at the top portion of fins due to deep Si etch at small space. In addition, tall fins tend to stick to each other after post etch wet clean due to surface tension and hydrophilic fin sidewall. In this publication, 200nm tall fins with straight profile at the significant top portion of fins are demonstrated by using multi cycles of passivation and etch process. Physical and chemical parameters of each cycle were tuned respectively to generate straight top profile for gate channel control and smooth bottom profile to make it friendly for the following oxide gap fill process. Intra-cell and iso-dense depth loading is less than 3% of total depth. In addition, fin sticking is no longer observed after this multi cycle process. The exact mechanism is still under investigation but it is postulated that the fin sidewall surface condition has changed to be less hydrophilic due to multi cycle passivation.

Current challenges are outlined for masking materials that enable future high aspect ratio (AR> 25) etch requirements. At such high aspect ratios, and 20nm to 30nm feature sizes, ion energy flux loss due to sidewall collisions, feature gap necking, polymerization, and feature charging in deep via-like structures has driven etch process conditions into very high bias voltage regimes. At these ion energies (keV), lateral removal of mask material due to faceting is the dominating mask erosion mechanisms. Using carbon as our baseline hard mask film, we present here normalized performance comparisons of 13 alternative films. We demonstrate that feature CD changes that correlate to lateral mask loss on the test structure also correlate to lateral mask loss on a real patterned structure and that we can therefore use these test structures as a tool for hard mask film evaluation without having the capability to pattern the hard mask under investigation. We propose that such test structures can be a valuable tool for film development as they relate to hard mask applications in dry etch patterning, and should be used in future development efforts rather than the more classical methods of blanket etch rate analysis. Such test structures can also be used to study film etch properties in general and we show that they are capable of capturing ARDE and sputter redeposition phenomena. Correlations between surface loss/addition as a function of sidewall position are presented and results of in-practice applications are shown. Key issues for future hard mask film implementation are discussed from the perspective of photo patterning, dry etching, wet etching, and integration.

In this paper we report on the patterning challenges for the integration of Spin-Transfer Torque Magneto-Resistive- Random-Access Memory (STT MRAM). An overview of the different patterning approaches that have been evaluated in the past decade is presented. Plasma based etching, wet echting, but also none subtractive pattering approaches are covered. The paper also reports on the patterning strategies, currently under investigation at imec.

A new type of plasma source (RLSA^TM) is described to generate low temperature plasma in the wafer region. The low T_e characteristic arises from decoupling of wafer region palsma from the power deposition region. This new plasma source has been demonstrated to show improved performance in etching high aspect ratio structures with reduced micro-loading and ARDE and can help mitigate challenges in advanced finFET FEOL etch applications.

Pulsed plasmas have been proposed many years ago by research labs and have shown a great potential for etch process improvement. Nevertheless, they have been introduced in manufacturing only recently and the exact characteristics of pulsed plasmas in industrial scale reactors are hardly known. In this paper, we have characterized silicon etching in pulsed HBr/O₂ plasmas using advanced plasma diagnostics (mass spectrometry and ion flux probe) in a 300 mm industrial reactor. We show that pulsing the plasma at low duty cycle reduces the gas molecules dissociation and plasma temperature, as well as the flux of energetic ions to the wafer. The ions during silicon etching are mostly silicon-containing ions that are heavier at low duty cycle. Silicon patterns etched using pulsed plasmas present improved profiles, which is attributed to more uniform passivation layers at low duty cycle.

In this paper, we present a cut-process overlay yield model for self-aligned multiple patterning and study how its yield will be affected by the overlay errors and cut-hole overhang. A geometric model is developed to identify the yield-related structures and construct the probability-of-failure (POF) functions. A general formula to calculate the cut-process overlay yield is derived using the joint POF function. Our calculation results show that an optimal cut-hole overhang must be found in order to achieve the maximum yield. The scaling tendency of the cut-process overlay yield is also studied, and it is found to be a potential challenge when the half pitch of device features reaches 7nm. The yields of 4-mask 193i and single-mask EUV cut modules are also calculated for a comparison. Moreover, a post-lithography misalignment correction technique based on dry etching is proposed. A geometric tilted etching model is developed to predict the relation between the tilting angle of an etching process and the shifted distance of the etched structure’s mass center.

We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.

Double Patterning process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device[1], and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pitch-Quadrupling (SAQP) achieved 11nm hp as introduced in previous our study[2]. Sa-MP has been required to mitigate a process complexity and cost impact. Furthermore, Process variability, Pattern fidelity, CD metrology for sub 20nm pattern also has to be considered. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened.

In this paper, we report a double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80nm and a lateral critical dimension (CD) below 30nm. We present a full stack for a double patterning approach for etch transfer down to a Si layer, including a hard mask in which the line and cut patterning are performed. The importance of the hard mask (HM) in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting straight profile. All the results shown in this paper have been obtained on 300mm wafers.

The advance of lithographic resolution has made it necessary to adopt extremely thin photoresist films for the fabrication of ‘2x nm’ structures in order to mitigate problems such as resist collapse during development but limiting achievable etch depths at the same time. By using multilayer hardmask stacks a considerable increase in achievable aspect ratio is possible. We have previously presented a fullerene based spin-on carbon hardmask material capable of high aspect ratio etching. Here we report our latest findings in material characterization of one of the original, and one new, formulations. By using a higher adduct derivative fullerene the solubility in industry-friendly solvents and thermal stability could be improved. The etching performance and materials characteristics of the new higher adduct fullerene hardmask were found to be comparable to the original hardmask.

Spin-on carbon (SOC) materials play an important role in the multilayer lithography scheme for the mass production of advanced semiconductor devices. One of the SOC’s key roles in the multilayer process (photoresist, silicon-containing hardmask, SOC) is the reactive ion etch (RIE) for pattern transfer into the substrate. As aspect ratios of the SOC material increase and feature sizes decrease, the pattern transfer from SOC to substrate by a fluorine-containing RIE induces severe pattern deformation (“wiggling”), which ultimately prevents successful pattern transfer into the substrate. One process that reduces line wiggling is a high-temperature (>250°C) post-application bake of the SOC material. In this study, we developed a process for evaluating SOC materials with respect to their pattern transfer performance. This process allowed us to evaluate line-wiggling behavior with several SOC materials at lower bake temperatures. This paper will discuss novel materials design in relation to high-aspect-ratio SOC layers and wiggling resistance.

New non-volatile memory, like RRAM, needs high aspect ratio (AR) bi-layer resist (BLR) pillar pattern to act as etch mask for sub-50 nm cell metal pillar definition [1]. HSQ/AR3 resist pillar is still not enough for patterning RRAM pillar since (1) AR is limited at ~7 which is still marginal in etching resistance, (2) BLR resist pillar CD is limited by dry development positive CD-bias, (3) BLR resist pillar is easy to collapse during venting to air, and (4) BLR resist pillar AR is lower for looser pillar densities which degrades the etching resistance. Tone reverse process flow for forming RRAM pillar is developed in this study to overcome these drawbacks. Thermal reflow assists the formation of sub-30 nm contact holes (C/Hs) on ZEP520A e-beam resist. Experimental results are summarized below. All the resolved CDs of C/H on ZEP520A with designed CD (DCD) of 40-100 nm are larger than 100 nm without proximity effect correction (PEC) on blank RRAM film stacking substrate. Smallest etched C/H on LTO after thermal reflow process is 14.4 nm. CD-bias of etched C/H on LTO relative to that of resist C/H after thermal reflow is larger for looser C/Hs. Thermal reflow of ZEP520A is C/H size before reflow, density, sidewall profile and reflow time dependent. NiOx hard mask is apparently without deposited into C/H smaller than 20 nm due to PVD deposition limit since the NiOx dot image disappeared after etching of LTO film for tone reverse. Smallest CD of TiN/Ti/HfOx RRAM pillar by tone reverse process flow is 28.8 nm using NiOx hard mask dot CD of 22.9 nm formed on 20.5 nm etched C/H on LTO after reflow. Uniform CD distribution of designed C/Hs result in uniformly distributed CDs after reflow / LTO etching / RRAM pillar formation. In summary, tone reverse process flow for RRAM pillar formation is successfully developed which has potential for patterning RRAM pillar of CD smaller than 20 nm in the help of NiOx hard mask deposition by atomic layer deposition (ALD) into oxide C/H in the future.

The characteristics of poly(methyl methacrylate) (PMMA) etching of self-assembled poly(styrene-block-methyl methacrylate) (PS-b-PMMA) thin film for forming a polystyrene (PS) mask were investigated. In this investigation, first, the etching selectivity of PMMA to PS under argon- and oxygen-plasma processes was evaluated. Higher selectivity was obtained in the case of argon plasma (3.9) compared to that of oxygen plasma (1.7). Second, to investigate the argon process in detail, the time dependence of etching depth was evaluated. It was found that PMMA etching rate decreases by more than half after etching to a depth of around 15 nm. To investigate the mechanism of this decrease in PMMA etching rate, the surface composition of PMMA was measured by X-ray photoelectron spectroscopy (XPS). The XPS result revealed that the reduction of etching rate is caused by a depletion of oxygen by argon ions, and the depleted oxygen attaches to the PMMA film in air exposure. In accordance with these results, to compensate the decrease in oxygen concentration, oxygen was added to the argon plasma at a composition of 1%. As a result of this oxygen addition, constant PMMA etching rate was confirmed, even beyond etching depth of 50 nm. It is thus concluded from these results that a PS lamellar mask pattern with a pitch from 25.5 to 70 nm could be successfully formed by using selective PMMA etching.

The migration to a 3D implementation for NAND flash devices is seen as the leading contender to replace traditional planar NAND architectures. However the strategy of replacing shrinking design rules with greater aspect ratios is not without its own set of challenges. The yield-limiting defect challenges for the planar NAND front end were primarily bridges, protrusions and residues at the bottom of the gates, while the primary challenges for front end 3D NAND is buried particles, voids and bridges in the top, middle and bottom of high aspect ratio structures. Of particular interest are the yield challenges in the channel hole process module and developing an understanding of the contribution of litho and etch defectivity for this challenging new integration scheme. The key defectivity and process challenges in this module are missing, misshapen channel holes or under-etched channel holes as well as reducing noise sources related to other none yield limiting defect types and noise related to the process integration scheme. These challenges are expected to amplify as the memory density increases. In this study we show that a broadband brightfield approach to defect monitoring can be uniquely effective for the channel hole module. This approach is correlated to end-of-line (EOL) Wafer Bin Map for verification of capability.

A dual hard mask concept for high resolution patterning has been evaluated with focus on highly selective etching processes for semiconductor manufacturing. The integration of thin SiO₂ and ZrO₂ hard mask materials enables highly selective patterning via plasma etch processes for future technology nodes. The patterning sequence is demonstrated for hole arrays with sizes down to 25 nm using a 50 nm thin resist which leads to the fabrication of trenches in silicon with aspect ratios up to 20:1. Alternative ZrO₂ based materials were investigated with focus on surface roughness reduction since it influences the final line etch roughness. Here Si-doped ZrO₂ (ALD) and spin-coatable ZrO₂ were compared to the pure and crystalline ZrO₂ as main selective material.

Electronics advancement demands integration of large number of transistors /capacitors in a very small chip area. Thus, small feature size fabrication is a critical issue and precise fabrications of features under nano scale require advanced lithographic and etching techniques. In this paper, MOS capacitor with TiN metal-gate and HfO₂ dielectric layer was fabricated in a world class clean-room lab in KTH. There, state-of-the art lithography stepper, advanced etching machines and all important clean-room fabrication facilities were used for successful fabrication of the nano-dimension MOS capacitor, whose detailed experimental procedures and results are exhaustively dealt in this report.