Open Access Presentation
10 April 2024 Lithography technology for memory device patterning
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Abstract
High density memory device has become an inevitable demand of processing capabilities and storage in various applications. The high-density memory devices been mainly developed by lithography, the lateral-scaling technology. In 2010s, DUV multi-patterning technique was introduced as a main contributor of the lateral-scaling, which however recently comes at the cost due to expanding of quadruple patterning and reduction of process margin. As a result, EUV lithography has joined into dominant patterning options for maximizing patterning resolution and reducing cost. This paper presents our latest patterning solutions extending patterning limit beyond sub 10nm, and outlook of future technologies on memory device patterning such as EUV, High-NA, 3D structure, and bonding overlay.
Conference Presentation
© (2024) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chan Hwang "Lithography technology for memory device patterning", Proc. SPIE PC12953, Optical and EUV Nanolithography XXXVII, PC1295303 (10 April 2024); https://doi.org/10.1117/12.3027044
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