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10 April 2024 Etch and integration challenges for microLED
Rino Marinelli, John O'Malley
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Proceedings Volume PC12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII; (2024) https://doi.org/10.1117/12.3013026
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States
Abstract
Mesa structures fabricated using a Plasma Etching process can introduce defects to the sidewalls & MQW region of a microLED display. Sidewall defects can increase the probability of non-radiative recombination losses especially in smaller pixel sizes. While ALE may be the emerging approach for uniform shallow low damage surface Etching, we can compare Mesa Sidewall conditions using both ALE and ICP principles Elevated etch electrode temperatures and/or radical dominated etches help, but the thermal budget has to be compatible with the upstream modules. Considerations of other contributors like mesa design or profile are also required. These decisions will impact the downstream integration, like dielectric conformality, generation of SiO2 voids during filling among others. This presentation will discuss uLED pixel output results relative to pixel size, shape & etching parameters. It will also show process integration challenges, how they were addressed and plans for future developments & improvements.
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Rino Marinelli and John O'Malley "Etch and integration challenges for microLED", Proc. SPIE PC12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, (10 April 2024); https://doi.org/10.1117/12.3013026
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KEYWORDS
Etching
Atomic layer etching
External quantum efficiency
Quantum processes
Internal quantum efficiency
Plasma
Quantum wells
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