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4 October 2024 Hardware implementation of a scalable two-spin Ising computer
Sidra Gibeault, Temitayo N. Adeyeye, Liam A. Pocher, Daniel P. Lathrop, Matthew W. Daniels, Mark D. Stiles, Jabez J. McClelland, William A. Borders, Jason T. Ryan, Philippe Talatchian, Ursula Ebels, Advait Madhavan
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Proceedings Volume PC13119, Spintronics XVII; PC1311924 (2024) https://doi.org/10.1117/12.3027885
Event: Nanoscience + Engineering, 2024, San Diego, California, United States
Abstract
Many probabilistic computing frameworks have been developed in recent years due to their potential as faster, energy-efficient alternatives to von Neumann computers for combinatorial optimization problems. In this work, we study the dynamics of a two-spin analog Ising computer implemented with superparamagnetic tunnel junctions (SMTJs). The operational-amplifier-based circuit features a polarity selection and a programmable gain parameter, allowing us to achieve both positive and negative coupling and perform simulated annealing if the gain is treated as inverse temperature. Experiments show that correlation between coupled SMTJs approaches 1 in the high-gain limit. Scaling of this design requires only trivial modifications to the circuit; however, scaling up to large networks of spins requires the development of SMTJs with enhanced properties, suggesting that a co-design approach between devices, architectures and algorithms is necessary.
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(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
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Sidra Gibeault, Temitayo N. Adeyeye, Liam A. Pocher, Daniel P. Lathrop, Matthew W. Daniels, Mark D. Stiles, Jabez J. McClelland, William A. Borders, Jason T. Ryan, Philippe Talatchian, Ursula Ebels, and Advait Madhavan "Hardware implementation of a scalable two-spin Ising computer", Proc. SPIE PC13119, Spintronics XVII, PC1311924 (4 October 2024); https://doi.org/10.1117/12.3027885
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KEYWORDS
Computer hardware
Algorithm development
Algorithms
Analog electronics
Computer programming
Design
Network architectures
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