Plasma-etch technology is an integral and indispensable part of patterning technology that has enabled continuous scaling in the semiconductor industry for several decades. The criticality of etch processes became even more apparent during the era when multiple patterning was used to advance scaling, while more recently it has been learned that a proper assessment of stochastic defects must include collection of data post-etch. Going forward, it is expected that etch technology will continue to be a critical part of nanopatterning, particularly for three-dimensional (3D) logic and memory devices, such as 3D FinFET, Gate All-Around (GAA) FET, 3D NAND flash memory as well as 3D dynamic random access memory (DRAM).

With this in mind, publication guidelines are provided in this editorial for papers where plasma-etch technology is central to the presented thesis. These guidelines aim to achieve a balance between the inclusion of key data in published papers and the protection of crucial proprietary information. For the parameters listed below, inclusion for most should be considered as a requirement when relevant to the paper. The etch process parameters can be considered as a possible exception, since it is understood that these are often quite sensitive for the authors’ organizations and sometimes cannot be published.

In some papers, post-etch data are included as important elements, but the etch processes themselves are not primary subjects of the papers. For such papers, a lower level of detail than what is specified below is adequate. However, the significance of data will be appreciated better by inclusion of detail, and authors of papers for which etch is not the primary subject should consider this when deciding what information to include.

Plasma-Etch Technology Guidelines