2 January 2024 Minimizing die fracture in 3DIC die integration
Jaime Bravo, Philippe Morey-Chaisemartin, Eric Beisser, Frederic Brault, Joshua Zusman, Jimmy Lefevre, Lifu Chang
Author Affiliations +
Abstract

Background

The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 μm have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.

Aim

We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).

Approach

Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product.

Results

The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point.

Conclusions

We show the feasibility of the implementation through EDA tools and outline the next step.

© 2024 Society of Photo-Optical Instrumentation Engineers (SPIE)
Jaime Bravo, Philippe Morey-Chaisemartin, Eric Beisser, Frederic Brault, Joshua Zusman, Jimmy Lefevre, and Lifu Chang "Minimizing die fracture in 3DIC die integration," Journal of Micro/Nanopatterning, Materials, and Metrology 23(1), 011003 (2 January 2024). https://doi.org/10.1117/1.JMM.23.1.011003
Received: 6 July 2023; Accepted: 16 October 2023; Published: 2 January 2024
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KEYWORDS
Semiconducting wafers

Silicon

Electronic design automation

Reliability

Image processing

Polymers

Wafer bonding

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