As the number of varied devices produced by a fab increase, coupled with an increased complexity in those devices which call for an ever increasing number of process layers, in- line process control via metrology can become an impossible task, unless metrology recipe management schemes are implemented. Logic fabs are now introducing more than 1 new device per day, which can result in the writing and management of thousands of recipes, which in turn can lead to the costly consumption of tool and personnel resources sand a general loss in productivity. In this paper we present the productivity gains to be made in the recipe creation process through off-line recipe generation, as well as a method of decreasing the recipe optimization time. We will also outline the concept of Just In Time recipe creation, its contribution to productivity gains, and its generalized implementation with respect to Overlay Metrology recipes.
As geometrical dimensions of semiconductor devices decrease, the need to introduce Cu processes into the fabrication cycle becomes increasingly important as a means of maintaining line resistances and circuit time constants. However, the success of implementing such as fabrication process is dependent on the ability to characterize it through quantitative means, such as Overlay metrology. In this paper we examine the overlay measurement results which have been obtained on a Cu based CMOS process at the 0.12 (Mu) m technology node. Overlay measurements were taken over a wide range of process conditions, and included wafers exhibiting extreme image contrast reversal, grainy conditions and low contrast. These factors have traditionally led to a decreased ability to make repeatable measurements, if the measurements could be made at all. Our results cover the important metrics of overlay metrology, and include precision, recipe portability, and measurement success rates. The results suggest that the overlay metrology issues encountered with such leading edge processes need not pose intractable barriers to obtaining reliable overlay metrology data.
The AMAG comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). This paper describes the result of an effort to benchmark six CD-SEM instruments according to this specification.
The Advanced Metrology Advisory Group (AMAG) comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). (Allgair, et al., 1998) This paper describes the results of an effort to benchmark six CD-SEM instruments according to this specification. The consensus among the AMAG metrologists was that many critical areas of performance of CD-SEMs required improvement. Following this assessment this specification for benchmarking was developed. The advanced CD-SEM specification addresses several critical areas for improvement, each with its own a separate section. The critical areas covered are: precision, accuracy, charging and contamination, performance matching, pattern recognition and stage navigation accuracy, throughput, and instrumentation outputs. Each section of the specification contains a concise definition of the respective performance parameter, and wherever appropriate refers to ISO definitions. The test methodology is described, complete with the relevant statistical analysis. Many parameters (including precision, matching, and magnification accuracy) are numerically specified to be consistent with the International Technology Roadmap for Semiconductors (ITRS, 1999). Other parameters, such as charging and linewidth accuracy, are targeted with guidelines for improvement. The test wafers developed for determining the level of compliance with the specification are also discussed. The AMAG circulated this report among the metrology instrument suppliers and conferred with them. Certain components of the specification have already been adopted by some of the manufacturers in their newer metrology instruments. International SEMATECH fabricated the AMAG test wafers described herein. Measurements on six state-of-the-art metrology instruments using the AMAG test wafers have been carried out and the results were processed according to this specification. A review of the results is presented in this paper.
Phase Profilometry (PP) has been proposed for in-situ/in-line critical dimension and profile measurements. This is usually accomplished by using rigorous electromagnetic theory to simulate the optical responses of gratings with different profiles, and by using spectroscopic ellipsometry/reflectometry to measure 1-D gratings. In this paper, phase profilometry is applied to the lithography process for cross-sectional profile extraction metrology. A focus-exposure experiment was conducted using Sematech's 193 nm lithography tool. Comparison between the measurements from CD-SEM, CD-AFM and PP are discussed and explained.
Conference Committee Involvement (8)
Metrology, Inspection, and Process Control for Microlithography XXIV
22 February 2010 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXIII
23 February 2009 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXII
25 February 2008 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXI
26 February 2007 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XX
20 February 2006 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XIX
28 February 2005 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XVIII
23 February 2004 | Santa Clara, California, United States
Metrology, Inspection, and Process Control for Microlithography XVII
24 February 2003 | Santa Clara, California, United States
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