Mr. José Andrés Otero Marnotes Profile

José Andrés Otero Marnotes

at Univ Politécnica de Madrid

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Publications (3)

Proceedings Article | 28 May 2013 Paper

Architectural evaluation of dynamic and partial reconfigurable systems designed with DREAMS tool

Andrés Otero, Ángel Gallego, Eduardo de la Torre, Teresa Riesgo

Proceedings Volume 8764, 87640H (2013) https://doi.org/10.1117/12.2021271

KEYWORDS: Computer aided design, Logic, Human-machine interfaces, Telecommunications, Field programmable gate arrays, Visualization, Virtual reality, Clocks, Manufacturing, Computer architecture

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Proceedings Article | 3 May 2011 Paper

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

A. Otero, M. Llinás, M. Lombardo, Jorge Portilla, E. de la Torre, T. Riesgo

Proceedings Volume 8067, 806706 (2011) https://doi.org/10.1117/12.887498

KEYWORDS: Field programmable gate arrays, Logic, Clocks, Error control coding, Control systems, Embedded systems, Sensor networks, Digital signal processing, Chemical elements, Manufacturing

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Proceedings Article | 3 May 2011 Paper

Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation

T. Cervero, A. Otero, E. de la Torre, S. López, G. Callicó, T. Riesgo, R. Sarmiento

Proceedings Volume 8067, 80670K (2011) https://doi.org/10.1117/12.887951

KEYWORDS: Scalable video coding, Field programmable gate arrays, Clocks, Video, Standards development, Electroluminescence, Neodymium, Image processing, Chemical elements, Computer programming

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