Extreme ultraviolet (EUV) lithography at 13.5 nm stands at the crossroads of next generation patterning technology for high volume manufacturing of integrated circuits. Photo resist models that form the part of overall pattern transform model for lithography play a vital role in supporting this effort. The physics and chemistry of these resists must be understood to enable the construction of accurate models for EUV Optical Proximity Correction (OPC). In this study, we explore the possibility of improving EUV photo-resist models by directly correlating the parameters obtained from experimentally measured atomic scale physical properties; namely, the effect of interaction of EUV photons with photo acid generators in standard chemically amplified EUV photoresist, and associated electron energy loss events. Atomic scale physical properties will be inferred from the measurements carried out in Electron Resist Interaction Chamber (ERIC). This study will use measured physical parameters to establish a relationship with lithographically important properties, such as line edge roughness and CD variation. The data gathered from these measurements is used to construct OPC models of the resist.
For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.
Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared
to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end
minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE.
This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to
find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID.
Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for
SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.
The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.
Model-based assist-feature (MBAF) placement has been shown to have considerable lithographic benefits vs. rule-based
assist-feature (RBAF) placement for advanced technology-node requirements. For very strong off-axis illumination,
MBAF-placement methods offer improved process window, especially for so-called forbidden pitch regions, and greatly
simplified tuning of AF-placement parameters. Historically, however, MBAF-placement methods had difficulties with
full-chip runtime, friendliness to mask manufacturing (e.g., mask rule checks or MRCs), and methods to ensure that
placed AFs do not print on-wafer. Therefore, despite their known limitations, RBAF-placement methods were still the
industry de facto solution through the 45 nm technology node. In this paper, we highlight recent manufacturability
advances for MBAFs by a detailed comparison of MBAF and RBAF methods. The MBAF method employed uses
Inverse Mask Technology (IMT) to optimize AF placement, size, shape, and software runtime, to meet the production
requirements of the 28 nm technology node and below. MBAF vs. RBAF results are presented for process window
performance, and MBAF vs. OPC results are presented for full-chip runtimes. The final results show that MBAF
methods have process-window advantages for technology nodes below 45 nm, with runtimes that are comparable to
OPC.
Inverse imaging has been long known to provide a true mathematical solution to the mask
design problem. However, it is often times marred by problems like high run-time, mask
manufacturability costs, and non-invertible models. In this paper, we propose a mask synthesis
flow for advanced lithography nodes, which capitalizes on the inverse mask solution while still
overcoming all the above problems. Our technique uses inverse mask technology (IMT) to
calculate an inverse mask field containing all the useful information about the AF solution. This
field is fed to a polygon placement algorithm to obtain initial AF placements, which are then cooptimized
with the main features during an OPC/AF print-fix routine to obtain the final mask
solution. The proposed flow enables process window maximization via IMT while guaranteeing
fully MRC compliant masks. We present several results demonstrating the superiority of this
approach. We also compare our IMT-AFs with the best AF solution obtained using extensive
brute-force search (via a first principles simulator, S-litho), and prove that our solution is
optimum.
A challenge in model-based assist feature placement is to find optimal placements while satisfying
mask rules and preventing AF printing. There are numerous strategies for achieving this ranging
from fully rule-based methods to pixel-based inversion. Our proposed solution is to identify the
optimal locations of assist features using modeling information based strictly on optics and resist
stack optical characteristics. Once these positions have been found, preliminary AFs can be placed.
At this point suggested sizes and shapes can be identified, although these can later be modified. In a
later step, MRC cleanup, printability fixing, and main-pattern OPC can be performed simultaneously.
This has the advantage of allowing the use of the full process model to predict the location of OPC
edges accurately, and use calibrated or 3d mask models to determine assist feature printing behavior.
This correction is done while maintaining MRC constraints. In this flow, an AF placement field,
generated from the pre-OPC target patterns, can be used to provide accurate guidance on how to
move assist features to get the most benefit while keeping other constraints in mind. Using this
method, a range of printability fixing strategies, guided by placement benefits, is available. We
present data showing that the benefit of AF placements can be determined from optical parameters,
on target (non-OPC) data, and that this method leads to beneficial yet compliant masks.
The continuing reduction in feature dimensions and tightening of process constraints have led to an
increasing demand for model-based approaches, which can efficiently explore the AF solution
space, and achieve AF configurations not easily accessible via rules. In this work, we approach the
AF placement problem as an inverse imaging problem. We discuss the generation of an inverse
mask field and its use in determining the assist feature location. The results are compared with the
single iteration intensity-field based AF placement with regard to symmetry, speed, memory,
convergence, and accuracy. Several results with different pitches and illumination conditions are
presented to demonstrate the robustness and adaptability of the inverse mask AF placement.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
Delays in equipment availability for both Extreme UV and High index immersion have led to a growing
interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves
decomposing a layout into two masking layers that are printed and etched separately so as to provide the
intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive
node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so
a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of
layout can be clearly identified and avoided based on short range interactions, compliance issues can also
extend over large areas of the design and are hard to recognize. This means certain design practices should
be implemented to provide suitable breaks or performed with layout tools that are double patterning
compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at
the minimum design space rather than the relaxed space intended. Another equally important class of
compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process
window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often
presented with multiple options for where to cut the design thereby defining an area of overlap between the
different printed layers. While these overlap areas can have markedly different topologies (for instance the
overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap
ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which
cannot be decomposed or which can only be decomposed with poor manufacturability need to be
highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an
internally developed automated double pattern decomposition tool to investigate design compliance and
describes a number of classes of non-conforming layout. Tool results then provide help to the designer to
achieve robust design compliant layout.
KEYWORDS: Model-based design, Atrial fibrillation, Optical proximity correction, Systems modeling, Image processing, Photomasks, Process modeling, System on a chip, Optical components, Image resolution
Demanding process window constraints have increased the need for effective assist feature placement algorithms that are robust and flexible. These algorithms must also allow for quick ramp up when changing nodes or illumination conditions. Placement based on the optical components of real process models has the potential to satisfy all of these requirements. We present enhancements to model-based assist feature algorithms. These enhancements include exploration of image-processing techniques that can be exploited for contact-via AF placement, model-based mask rule check (MRC) conflict resolution, the application of models to line-space patterns, and a novel placement technique for contact-via layers using a specially-built single modeling kernel.
The upcoming 45nm and 32nm device generations will continue the familiar industry lithography trends of
decreased production K1 factor, reduced focus error tolerances and increased pattern density. As previous
experience has shown, small changes in the values of lithographic K1, focus tolerance and pattern density
for the process-design space can lead to large required changes in OPC and RET solutions. Therefore,
significant improvements in utility and speed are needed for these new device generations. In this paper we
highlight significant new functionality and performance capabilities using existing Field-based OPC and
RET methods. The use of dense grid calculations in Field-based methods is shown to provide a software
platform for robust and fast implementation of new model-based RET techniques such as model-based
assist feature placement and tuning. We present the performance and capability increases for model-based
RET methods. Additionally, we have studied and present the performance of production 45nm generation
field-based OPC and RET software across several different multiple-purpose hardware platforms.
Significant improvements in runtime (for approximately the same hardware cost) are observed with new
general purpose hardware platforms and with software optimization for this hardware.
Sub-Resolution Assist Features (SRAFs) are placed into patterns to enhance the through process imaging performance of
critical features. SRAFs are typically placed using complex rules to achieve optimal configurations for a pattern.
However, as manufacturing process nodes are growing increasingly complex, the SRAF placement rules will most likely
be unable to produce optimal performance on some critical features. A primary impediment to resolving these problems
is identifying poorly performing features in an efficient manner.
A new process model form referred to as a Focus Sensitivity Model (FSM) is capable of rapidly analyzing SRAF
placement for through process pattern performance. This study will demonstrate that an FSM is capable of finding suboptimal
SRAF placements as well as missing SRAFs. In addition, the study suggests that the FSM does not need to
comprehend the entire photolithography process to analyze SRAF placement. This results in simpler models that can be
generated before a manufacturing process enters its development phase.
Sub-resolution assist features (SRAFs) are an important tool for improving through-process robustness of advanced lithographic processes. Assist features have generally been placed and adjusted according to heuristic rules. The complexity of these rules increases rapidly with shrinking features size requiring more wafer data for calibration and more effort on the part of engineers. For advanced nodes, a model-based approach may better account for the variety of two-dimensional geometries and reduce substantially the amount of user effort required for effective SRAF placement. There are many ways in which model-based methods can be used to improve the effectiveness of assist features; we investigate several here. In the investigations described here, process window models may be employed to: 1) derive optimal rules for initial AF placement in a rule-based process, 2) resolve mask rule violations in optimal ways, and 3) make post-placement corrections of mask sites with poor behavior. In addition, we discuss a method for replacing an initial rule-based assist feature placement with a model-based placement which can consider the local two-dimensional geometry.
Sub-resolution assist features are an important tool for improving process robustness for one-dimensional pattern features at advanced manufacturing process nodes. However, sub-resolution assist feature development efforts have not generally considered optimization for process robustness with two-dimensional pattern features. This generally arises both from conservatively placing SRAFs to avoid the possibility of imaging, and from a desire to simplify SRAF placement rules. By studying two-dimensional features using a manufacturing sensitivity model, one can gain insight into the capabilities of SRAFs regarding two-dimensional pattern features. These insights suggest new methodologies for shaping assist features to enhance two-dimensional feature robustness. In addition, a manufacturing sensitivity model form can be employed to optimize the placement of multiple competing SRAFs in localized two-dimensional regions. Initial studies demonstrate significant pullback reduction for two-dimensional features once SRAF placement has been optimized using the manufacturing sensitivity model form.
KEYWORDS: Control systems, Optical proximity correction, Data modeling, Process control, Data corrections, Image processing, Data centers, Process modeling, Model-based design, Systems modeling
Model based Optical Proximity Correction work is currently performed by segmenting patterns in a layout and iteratively applying corrections to these segments for a set number of iterations. This is an open loop control methodology that relies on a finely tuned algorithm to arrive at a proper correction. A goal of this algorithm is to converge in the fewest number of iterations possible. As technology nodes become smaller, different correction areas tend to correct at different rates, and these correction rates are diverging with process node. This leads to more iterations being required to converge to a final OPC solution, the consequence of which is an increased runtime and tapeout cost. The current solution to this problem is to use proportional damping factors to attempt to bring different structure types to a solution. Classical control theory provides tools to optimize the convergence of these processes and to speed up convergence in physical systems. Introducing derivative and integral control while continuing use of proportional control should reduce the number of iterations needed to converge to a final solution as well as optimize the convergence for varied configurations.
Mask fabrication costs are significantly aggravated by OPC complexity. This increased complexity is presumably needed to accurately render 2-D configurations. The humble line-end is one of the most difficult 2-D configurations to print accurately, when considering process margin requirements and mask fabrication constraints. In this paper, the requirements for proximity corrected line-end structures will be explored and a pattern complexity metric will be proposed to compare relative mask cost versus line-end lithographic performance. Many types of correction shapes are available to improve process margin for line-ends. However, the cost of producing these various line-end configurations can vary dramatically. Using both a simple optical model to simulate line-end performance through focus offset and a cost metric based on fracture shots, a comparison of six types of lines ends for correction and process efficiency will be undertaken. Each of the six line-end corrections will attempt to produce equally effective silicon line-end shapes. Line-ends will be evaluated based on shortening (pullback), pinching, and bridging characteristics. Line-end lithographic behavior will be characterized through all process window boundary conditions. The objective of this study is to quantify the tradeoffs among three variables: mask cost, process-window robustness, and design tolerance margin. In addition, through the study of proximity effects on the various line-end types, the possibility of mixing expensive but high performance line-ends with simpler less aggressive line-ends to reduce reticle cost while maintaining or increasing correction fidelity will be studied.
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