Dr. Chang-Min Park Profile

Dr. Chang-Min Park

Principal Engineer at SAMSUNG Electronics Co Ltd

SPIE Involvement:

Author

Publications (25)

Proceedings Article | 21 November 2023 Presentation + Paper

Analysis method to define photoresist resolution in EUV lithography

Yongbeom Seo, Heeyoung Go, Jinseong Lee, Taehwan Oh, Donghun Shin, Huiseob Shin, Jisun Lee, Sangjin Kim, In-sung Kim, Changmin Park

Proceedings Volume 12750, 127500B (2023) https://doi.org/10.1117/12.2687461

KEYWORDS: Extreme ultraviolet lithography, Critical dimension metrology, Stochastic processes, Optical lithography, Bridges, Scanning electron microscopy, Resistance, Photoresist materials, Extreme ultraviolet, Metals

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Proceedings Article | 21 November 2023 Presentation + Paper

Rigorous 3D probabilistic computational lithography and chip-level inspection for EUV stochastic failure detection

Eunju Kim, Wooseok Kim, Jonggwan Lee, Seongjong Kim, Sukyong Lee, Nohong Kwak, Mincheol Kang, Yongchul Jeong, Myungsoo Hwang, Chang-Min Park, Kyoil Koo, Seongtae Jeong, John Biafore, Mark Smith, Trey Graves, Anatoly Burov, Pradeep Vukkadala, Guy Parsey, Cao Zhang, Kunlun Bai, Janez Krek, Craig Higgins, Sergei Bakarian, Kyeongeun Ko, Roel Gronheid, Kaushik Sah, Andrew Cross, Yi Liu, Alessandro Vaglio Pret, Chris Walker, Vikram Tolani, George Hwa, Peter Hu, Chang Song, Alex Arkhipov, Loemba Bouckou, Chi-Ping Liu, Xiaochun Yang, Kana O'Hara, Donghwan Son

Proceedings Volume 12750, 127500C (2023) https://doi.org/10.1117/12.2687373

KEYWORDS: Stochastic processes, Inspection, Extreme ultraviolet, Computational lithography, Printing, Semiconducting wafers, Photoresist materials, Extreme ultraviolet lithography, Statistical analysis, Physical phenomena

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Proceedings Article | 28 April 2023 Presentation + Paper

An investigation on the process control for the solid application of EUV MOR

Sangjin Kim, Il-Hwan Kim, Hyungju Ryu, Yongbeom Seo, Yigwon Kim, Jinhee Jang, Tae-Min Choi, Sol Jeong, Yongchul Jeong, Kyoungyong Cho, Cheolin Jang, Kyeongbeom Park, Changmin Park

Proceedings Volume 12494, 124940V (2023) https://doi.org/10.1117/12.2658345

KEYWORDS: Etching, Extreme ultraviolet lithography, Metal oxides, Coating, Chemical reactions, Process control, Extreme ultraviolet

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Proceedings Article | 28 April 2023 Presentation + Paper

Chemical approach to make the most of EUVL: stochastic effect mitigation with developer and rinse

Hyungju Ryu, Dokyeong Kwon, Jiho Song, Wongi Park, Jinseong Gwak, Haram Ko, Jiyoung Lee, Jinpyoung Kim, Kyungseok Ryu, Sungjo Hwang, Taemin Jeong, Heeyoung Go, Yigwon Kim, Kyoungyong Cho, Sangjin Kim, Changmin Park

Proceedings Volume 12494, 1249404 (2023) https://doi.org/10.1117/12.2656415

KEYWORDS: Extreme ultraviolet, Stochastic processes, Extreme ultraviolet lithography, Lithography, Optical lithography, Photoresist processing, EUV optics, Chemical composition, Semiconductors

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Proceedings Article | 27 April 2023 Presentation + Paper

SEM ADI on device overlay: the advantages and outcome

Sangho Jo, Jongsu Kim, Youngsik Park, Muyoung Lee, Jinhong Park, Changmin Park, Jeong-Ho Yeo, Yaniv Abramovitz, You Jin Kim, Asaf Shoham, Shmuel Ben Nissim

Proceedings Volume 12496, 124960K (2023) https://doi.org/10.1117/12.2657672

KEYWORDS: Scanning electron microscopy, Overlay metrology, Semiconducting wafers, Scanners, Optical parametric oscillators, Measurement devices, Lithography, Error control coding, Optical alignment, Metrology

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The advanced logic node is continuously shrinking toward sub-nm node and EUV lithography is the one of main drivers to reach better patterning resolution resulting in reduced process steps. Along with this design rule shrink, On Product Overlay (OPO) requirement has been critical to the device yield making the accuracy and stability of optical overlay measurement to become primary concern on the lithography process control. Historically Optical Microscope (OM) ADI overlay was accepted and the standard for control to meet OPO requirements. Along the past years, as OPO budget diminishes with node-to-node, OM overlay required additional supporting reference data to compensate the inherent accuracy problem. Industry adopted the accuracy correction knob with High Voltage SEM (HV-SEM) at post etch, also known as SEM AEI overlay. The SEM AEI overlay measures the error contribution of different process influence and the overlay mark to real device pattern overly bias together. The inaccuracy of OM ADI overlay has been treated as a non-correctable error components till the on-device overlay measurement of HV-SEM after etching was enabled to compensate the delta known as Non-Zero Offset (NZO) or Mis-Reading Correction (MRC). Today the HV-SEM on-device overlay measurement at AEI is widely adopted as one of critical component to meet the OPO requirement enabling scaling for all types of advanced CMOS devices production. The main driver of On-Device-Overlay (ODO) measurement at AEI step is the see-through imaging capability to see all relevant layers through the stack even though the measurement step/time differs on the same wafer of the ADI optical overlay measurement are ranging from few to two-digit days depending on the process complexity. There has been an increasing need for a faster response of overlay measurements to close the overlay control loop and breakdown the device to target error versus the process overly induce component – in other words, to correct in the right step. This leads to the necessity of SEM ADI overlay measurement. With the recent e-Beam evolution of more higher landing energy, probe current and improved Total Measurement Uncertainty (TMU) performance, SEM ADI overlay measurement is enabled and considered to show the performances to meet market requirements on the selected layers of interest. In this paper, we would like to demonstrate the enablement of SEM ADI overlay measurement including the accuracy comparison with OM ADI overlay on the DBO scribe target versus real device pattern measurement performance. With SEM ADI and AEI overlay measurement on the same patterns, we could also demonstrate the error breakdown between optical target to device and from ADI to AEI process induced error which will enable the better correctable methodology to minimize NZO/MRC. In addition, this process contribution to error breakdown could be extended to improve, in the future, the Edge Placement Error (EPE) control.

Proceedings Article | 26 February 2021 Presentation + Paper

28nm pitch single exposure patterning readiness by metal oxide resist on 0.33NA EUV lithography

D. De Simone, L. Kljucar, P. Das, R. Blanc, C. Beral, J. Severi, N. Vandenbroeck, P. Foubert, A. Charley, A. Oak, D. Xu, W. Gillijns, J. Mitard, Z. Tokei, M. van der Veen, N. Heylen, L. Teugels, Q. T. Le, F. Schleicher, P. Leray, K. Ronse, Il Hwan Kim, Insung Kim, Changmin Park, Jisun Lee, Koungmin Ryu, P. De Schepper, J. Doise, M. Kocsis

Proceedings Volume 11609, 116090Q (2021) https://doi.org/10.1117/12.2584713

KEYWORDS: Extreme ultraviolet lithography, Optical lithography, Oxides, Metals, Extreme ultraviolet, Scanners, Scanning electron microscopy, Photoresist processing, Lithography, Line edge roughness

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For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.

Proceedings Article | 24 March 2017 Open Access

Progress in EUV lithography toward manufacturing

Seong-Sue Kim, Roman Chalykh, Hoyeon Kim, Seungkoo Lee, Changmin Park, Myungsoo Hwang, Joo-On Park, Jinhong Park, Hocheol Kim, Jinho Jeon, Insung Kim, Donggun Lee, Jihoon Na, Jungyeop Kim, Siyong Lee, Hyunwoo Kim, Seok-Woo Nam

Proceedings Volume 10143, 1014306 (2017) https://doi.org/10.1117/12.2264043

KEYWORDS: Extreme ultraviolet lithography, Manufacturing, Extreme ultraviolet, Pellicles, Photomasks, Transmittance, Logic, Scanners, Reticles, Chemical elements

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Proceedings Article | 17 April 2014 Paper

Prospects of DUV OoB suppression techniques in EUV lithography

Chang-Min Park, Insung Kim, Sang-Hyun Kim, Dong-Wan Kim, Myung-Soo Hwang, Soon-Nam Kang, Cheolhong Park, Hyun-Woo Kim, Jeong-Ho Yeo, Seong-Sue Kim

Proceedings Volume 9048, 90480S (2014) https://doi.org/10.1117/12.2046132

KEYWORDS: Deep ultraviolet, Extreme ultraviolet, Extreme ultraviolet lithography, Photomasks, Scanners, Pellicles, Reflectivity, Semiconducting wafers, Particles, Etching

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SPIE Journal Paper | 18 March 2013

Mask characterization for critical dimension uniformity budget breakdown in advanced extreme ultraviolet lithography

Peter Nikolsky, Chris Strolenberg, Rasmus Nielsen, Tjitte Nooitgedacht, Natalia Davydova, Greg Yang, Shawn Lee, Chang-Min Park, Insung Kim, Jeongho Yeo

JM3, Vol. 12, Issue 02, 021006, (March 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.2.021006

KEYWORDS: Photomasks, Reticles, Critical dimension metrology, Semiconducting wafers, Extreme ultraviolet lithography, Extreme ultraviolet, Cadmium, Reflectivity, Scanners, Semiconductors

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As the International Technology Roadmap for Semiconductors critical dimension uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. We will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for advanced extreme ultraviolet (EUV) lithography with 1D (dense lines) and 2D (dense contacts) feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CDs and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples. Mask stack reflectivity variations should also be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We also observed mask error enhancement factor (MEEF) through field fingerprints in the studied EUV cases. Variations of MEEF may play a role towards the total intrafield CDU and may need to be taken into account for EUV lithography. We characterized MEEF-through-field for the reviewed features, with results herein, but further analysis of this phenomenon is required. This comprehensive approach to quantifying the mask part of the overall EUV CDU contribution helps deliver an accurate and integral CDU BB per product/process and litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps extend the limits of Moore’s Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Proceedings Article | 8 November 2012 Paper

Mask characterization for CDU budget breakdown in advanced EUV lithography

Peter Nikolsky, Chris Strolenberg, Rasmus Nielsen, Tjitte Nooitgedacht, Natalia Davydova, Greg Yang, Shawn Lee, Chang-Min Park, Insung Kim, Jeong-Ho Yeo

Proceedings Volume 8522, 85220P (2012) https://doi.org/10.1117/12.970395

KEYWORDS: Photomasks, Reticles, Semiconducting wafers, Extreme ultraviolet, Extreme ultraviolet lithography, Critical dimension metrology, Scanners, Reflectivity, Cadmium, Semiconductors

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As the ITRS Critical Dimension Uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and a high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. In this paper we will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for an advanced EUV lithography with 1D and 2D feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CD’s and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples in this paper. Also mask stack reflectivity variations should be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We observed also MEEF-through-field fingerprints in the studied EUV cases. Variations of MEEF may also play a role for the total intrafield CDU and may be taken into account for EUV Lithography. We characterized MEEF-through-field for the reviewed features, the results to be discussed in our paper, but further analysis of this phenomenon is required. This comprehensive approach to characterization of the mask part of EUV CDU characterization delivers an accurate and integral CDU Budget Breakdown per product/process and Litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps to extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Proceedings Article | 14 October 2011 Paper

30nm full field quartz template replicated from Si master for FLASH active layer NIL

Duhyun Lee, Byung-Kyu Lee, Woong Ko, Jae-Kwan Kim, Kiyeon Yang, Byounghoon Seung, Ilyong Jang, Mun Ja Kim, Byunggook Kim, ChangMin Park, Jeongho Yeo, Changyoul Moon

Proceedings Volume 8166, 81661U (2011) https://doi.org/10.1117/12.898747

KEYWORDS: Quartz, Silicon, Etching, Nanoimprint lithography, Chromium, Oxides, Photomasks, Line width roughness, Electron beam lithography, Semiconducting wafers

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Proceedings Article | 8 April 2011 Paper

Availability of underlayer application to EUV process

Hitoshi Kosugi, Carlos Fonseca, Fumiko Iwao, Hiroshi Marumoto, Hyun-Woo Kim, Kyoungyong Cho, Cheol-Hong Park, Chang-Min Park, Hai-Sub Na, Cha-Won Koh, Hanku Cho

Proceedings Volume 7969, 79692E (2011) https://doi.org/10.1117/12.878730

KEYWORDS: Coating, Semiconducting wafers, Contamination, Extreme ultraviolet, Data modeling, Calibration, Extreme ultraviolet lithography, Scanning electron microscopy, Etching, Thin films

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Proceedings Article | 7 April 2011 Paper

LWR improvement in EUV resist process

Chawon Koh, Hyun-Woo Kim, Sumin Kim, Hai-Sub Na, Chang-Min Park, Cheolhong Park, Kyoung-Yong Cho

Proceedings Volume 7969, 796918 (2011) https://doi.org/10.1117/12.879334

KEYWORDS: Line width roughness, Extreme ultraviolet, Extreme ultraviolet lithography, Photoresist processing, Critical dimension metrology, Etching, Inspection, Electronics, Optical lithography, Semiconductors

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Extreme ultraviolet lithography (EUVL) is the most effective way to print sub-30 nm features. The roughness of both the resist sidewall (line width roughness [LWR]) and resist top must be overcome soon for EUVL to be implemented. Currently, LWR can vary by about 1 nm according to the recipe used. We have characterized two promising techniques to improve LWR, an EUV rinse/TBAH process and an implant process, and demonstrated their efficacy. After cleaning inspection (ACI), LWR was improved with both the rinse and implant processes. After development inspection (ADI), LWR improved (0.12 nm, 2.4%) and ACI LWR improved (0.1 nm, 2.0% improvement) after using the EUV rinse process. ADI and ACI LWR improvement (0.45 nm, 9.1%, and 0.3 nm, 6.9%, respectively) was demonstrated with the EUV rinse/TBAH process. ADI LWR improvement (0.5 nm, 8.1%) and ACI LWR improvement (-0.5 nm, -16.9%) were characterized with the implant process. Critical dimension (CD) showed similar changes through pitch after the EUV rinse or TBAH process, but the degree of change depended on the initial pattern size giving CD difference of 2 nm between 30 nm HP and 50 nm HP after the implant process. For this technique, the dependence of CD change on pattern size must be minimized. Further extensive studies with rinse or implant are strongly encouraged for continued LWR improvement and real process implementation in EUVL. Demonstrating <2.2 nm LWR after pattern transfer is important in EUVL and needs to be pursued using various technical approaches. Initial resist LWR is important in assessing LWR improvements with additional process techniques. An initial EUV LWR < ~5.0 nm is required to properly assess the validity of the technique. Further study is required to improve ADI LWR and maintain better LWR after etch with advanced EUV rinse materials. Defects also need to be confirmed following the EUV rinse and TBAH developer. Further developing the implant process should focus on LWR improvement at low frequencies and optimization of process conditions to maintain the EUV resist profile and resist height. The dependence of CD change on pattern size likewise needs to be minimized.

Proceedings Article | 7 April 2011 Paper

CD uniformity improvement for EUV resists process: EUV resolution enhancement layer

Hyun-Woo Kim, Hai-Sub Na, Chang-Min Park, Cheolhong Park, Sumin Kim, Chawon Koh, In-Sung Kim, Han-Ku Cho

Proceedings Volume 7969, 796916 (2011) https://doi.org/10.1117/12.879791

KEYWORDS: Extreme ultraviolet, Critical dimension metrology, Deep ultraviolet, Reflectivity, Extreme ultraviolet lithography, Line width roughness, Photoresist processing, Resolution enhancement technologies, Photomasks, Plasma

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Proceedings Article | 3 April 2010 Paper

Nanoimprint template fabrication using wafer pattern for sub-30nm

C. Park, K. Kim, Y. Lee, K. Cho, J. Park, In Kim, J. Yeo, S. Choi, D. Lee, B. Lee, S. Hwang

Proceedings Volume 7637, 76371R (2010) https://doi.org/10.1117/12.846481

KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Electron beam lithography, Lithography, Line width roughness, Etching, Photomasks, Silicon, Optical lithography, Quartz

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Proceedings Article | 20 March 2010 Paper

The analysis of EUV mask defects using a wafer defect inspection system

Kyoung-Yong Cho, Joo-On Park, Changmin Park, Young-Mi Lee, In-Yong Kang, Jeong-Ho Yeo, Seong-Woon Choi, Chan-Hoon Park, Steven Lange, SungChan Cho, Robert Danen, Gregory Kirk, Yeon-Ho Pae

Proceedings Volume 7636, 76361E (2010) https://doi.org/10.1117/12.846482

KEYWORDS: Semiconducting wafers, Photomasks, Line width roughness, Inspection, Wafer inspection, Scanning electron microscopy, Defect detection, Signal to noise ratio, Extreme ultraviolet lithography, Line edge roughness

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Proceedings Article | 20 March 2010 Paper

Patterning with EUVL: the road to 22nm node

Hyun-Woo Kim, Hai-Sub Na, Kyoung-Yong Cho, Chang-Min Park, Takahiro Yasue, Subramanya Mayya, Han-Ku Cho

Proceedings Volume 7636, 76360Q (2010) https://doi.org/10.1117/12.846474

KEYWORDS: Extreme ultraviolet, Extreme ultraviolet lithography, Line width roughness, Lithography, Deep ultraviolet, Polymers, Chemical reactions, Double patterning technology, Opacity, Photomasks

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Proceedings Article | 18 March 2009 Paper

Assessment of full-chip level EUV optical correction for sub-40nm memory device

Jeonghoon Lee, Insung Kim, Doohoon Goo, Joo-on Park, Changmin Park, Jinhong Park, Jeongho Yeo, Seongwoon Choi, Woosung Han

Proceedings Volume 7271, 727142 (2009) https://doi.org/10.1117/12.813996

KEYWORDS: Extreme ultraviolet lithography, Photomasks, Extreme ultraviolet, Optical proximity correction, Reflectivity, Scanners, Critical dimension metrology, EUV optics, Optical calibration, Cadmium

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Proceedings Article | 18 March 2009 Paper

The application of EUV lithography for 40nm node DRAM device and beyond

Joo-on Park, Chawon Koh, Doohoon Goo, InSung Kim, Changmin Park, Jeonghoon Lee, JinHong Park, JeongHo Yeo, Seong-Woon Choi, Chan-hoon Park

Proceedings Volume 7271, 727114 (2009) https://doi.org/10.1117/12.814001

KEYWORDS: Extreme ultraviolet lithography, Extreme ultraviolet, Lithography, Etching, Photomasks, Semiconducting wafers, Scanners, Optical proximity correction, Light sources, Resistance

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Proceedings Article | 4 December 2008 Paper

Methodology of flare modeling and compensation in EUVL

Insung Kim, Hoyoung Kang, Changmin Park, Joo-On Park, Jeonghoon Lee, Jinhong Park, Doohoon Goo, Jeongho Yeo, Seong-Woon Choi, Woosung Han

Proceedings Volume 7140, 714009 (2008) https://doi.org/10.1117/12.804673

KEYWORDS: Point spread functions, Fractal analysis, Extreme ultraviolet, Lithography, Optical proximity correction, Photomasks, Critical dimension metrology, Modulation transfer functions, Convolution, Cadmium

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Proceedings Article | 4 December 2008 Paper

CD uniformity improvement for 3x nm node devices

Chang-Min Park, Hyun-Byuk Kim, Hyung-Do Kim, Hyun-Woo Kim, Cheol-Hong Kim, Joo-On Park, Doohoon Goo, Jeongho Yeo, Seong-Woon Choi, Woo-Sung Han, Min-Su Choi, Sung-Woo Hwang

Proceedings Volume 7140, 714024 (2008) https://doi.org/10.1117/12.804627

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Photomasks, Double patterning technology, Lithography, Etching, Semiconductors, Control systems, Spatial resolution, Transistors

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Proceedings Article | 28 May 2004 Paper

Fulfillment of model-based OPC for contact patterns in 60-nm level logic device

Sang-Wook Kim, Sung-Woo Lee, Chang-Min Park, Soo-Han Choi, Young-Mi Lee, Yool Kang, Gi-Sung Yeo, Jung-Hyeon Lee, Han-Ku Cho, Woo-Sung Han

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.536268

KEYWORDS: Optical proximity correction, Logic devices, Model-based design, Critical dimension metrology, Instrument modeling, Data modeling, Transistors, Resistance, Materials processing, Optical lithography

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Proceedings Article | 14 May 2004 Paper

Realization of sub-80nm small space patterning in ArF photolithography

Si-Hyun Kim, Hyung-Do Kim, Si-Hyeung Lee, Chang-Min Park, Man-Hyoung Ryoo, Gi-Sung Yeo, Jung-Hyeon Lee, Han-Ku Cho, Woo-Sung Han, Joo-Tae Moon

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.536340

KEYWORDS: Photoresist processing, Optical lithography, Resolution enhancement technologies, Lithography, Semiconducting wafers, Etching, Optical proximity correction, Chemical reactions, Critical dimension metrology, Materials processing

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Proceedings Article | 1 August 2002 Paper

Characteristics of residues and optical change of HT PSM during stepwise wet cleaning and optimization of HT PSM cleaning process

Woo-Gun Jeong, Dae-Woo Kim, Chang-Min Park, Ki-Won An, Dong-Heok Lee, Jin-Min Kim, Sang-Soo Choi, Soo Hong Jeong

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476970

KEYWORDS: Etching, Inspection, Particles, Transmittance, Dry etching, Quartz, Neodymium, Scanning electron microscopy, Industrial chemicals, Defect inspection

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Proceedings Article | 10 January 2002 Paper

Effect of first information layer on second information layer in dual-layer disc

Kyung-Geun Lee, In-Oh Hwang, Chang-Min Park, Yoon-Gi Kim, In-Sik Park, Dong-Ho Shin

Proceedings Volume 4342, (2002) https://doi.org/10.1117/12.453413

KEYWORDS: Mirrors, Interference (communication), Digital video discs, Aluminum, Reflectivity, Digital electronics, Electronics, Holograms, Light sources, Quantitative analysis

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