Roughness cannot be ignored as feature sizes shrink with Moore's Law, since it has potential to influence the device's performance. The roughness is usually described by line edge roughness (LER) and line width roughness (LWR). LER is the deviation of a feature edge from its ideal shape and is defined as three times the standard deviation, the deviation from the average line width is defined as LWR. For a certain critical dimension (CD) and pitch, there are many factors that can contribute to the roughness in the lithography process, such as source, mask optimizations, photoresist types and its processing, etc. An in-depth insight of the roughness formation mechanisms is essential to improve LER. This study employs photoresist process simulation to analyze LER, offering an efficient alternative to silicon data collection. Simulation analysis is carried out to examine the key factors influencing LER, including quencher concentration, photoacid diffusion length, PEB temperature. Concurrently, the study also delves into the impact of photoresist resin molecular composition and the development process on roughness. By using simulation to understand and predict roughness, the research provides insights into optimizing lithography parameters, thereby improving process stability and minimizing roughness formation.
As increasing complexity of1 devices and scaling have continued to push the lithography to low k1 limit, lithographic scientists have been developing various resolution enhancement techniques (RET) to extend 193nm immersion lithography. Chrome-less phase shift mask (PSM) is one of the RET techniques which can produce frequency doubling to half the pitch. The shifter is changed from MoSi to quartz for chrome-less PSM. And the shifter in quartz that is challenging to control at mask etch process. This will cause phase error, lead to image shift and CD asymmetry impacts wafer CD uniformity (CDU) due to intensity imbalance. In this paper, based on aerial image simulations, the conditions to generate frequency doubling have been studied, the resolution limit of the frequency doubling has been investigated. The phase error tolerance of frequency doubling for accepted wafer CDU referring ITRS road map plus budget breakdown to reticle CDU contribution has been studied. The phase error tolerance for smaller pitch is predicted with polynomial fitting extend too.
Mask tape-out is a frequent job in wafer fabrication factories and research institutes. Frame generation is one of the important steps in mask tape-out flow. It requires extensive lithography, process integration, and mask tape-out experience; a large amount of manual work and various data preparation is included, especially when multiple products are combined into a single mask and all product conditions need to be fulfilled simultaneously. When more factors need to be considered, mistakes can be made. We develop a methodology to help frame generation, such as alignment and overlay mark design, selection and placement. It has demonstrated the ability to guide people in error-proofing work, support for frame GDS automatic generation and metrology recipe automatic generation. This is a user-friendly methodology that can reduce the frame generation difficulty and generation time from several weeks to a few minutes.
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