Mr. Edward Kah Ching Teoh Profile

Edward Kah Ching Teoh

at Motivo Inc

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Author

Publications (5)

Proceedings Article | 3 April 2017 Presentation + Paper

Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning

Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan

Proceedings Volume 10148, 1014808 (2017) https://doi.org/10.1117/12.2262146

KEYWORDS: Pattern recognition, Yield improvement, Computational lithography, Databases, Manufacturing, Integrated circuit design, Machine learning, Analytics, Integrated circuits, Design for manufacturability, Optical proximity correction, Product engineering, Lithography, Statistical analysis, Metrology, Computer simulations

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Proceedings Article | 26 March 2015 Paper

Design layout analysis and DFM optimization using topological patterns

Ji Xu, Karthik Krishnamoorthy, Edward Teoh, Vito Dai, Luigi Capodieci, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 9427, 94270Q (2015) https://doi.org/10.1117/12.2086904

KEYWORDS: Manufacturing, Metals, Design for manufacturing, Raster graphics, Image classification, Data modeling, Statistical analysis, Design for manufacturability, Current controlled current source, Optimization (mathematics)

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Proceedings Article | 28 March 2014 Paper

Systematic data mining using a pattern database to accelerate yield ramp

Edward Teoh, Vito Dai, Luigi Capodieci, Ya-Chieh Lai, Frank Gennari

Proceedings Volume 9053, 905306 (2014) https://doi.org/10.1117/12.2047307

KEYWORDS: Manufacturing, Image classification, Raster graphics, Databases, Image processing, Optical proximity correction, Silicon, Data mining, Tolerancing, Lithography

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Pattern-based approaches to physical verification, such as DRC Plus, which use a library of patterns to identify problematic 2D configurations, have been proven to be effective in capturing the concept of manufacturability where traditional DRC fails. As the industry moves to advanced technology nodes, the manufacturing process window tightens and the number of patterns continues to rapidly increase. This increase in patterns brings about challenges in identifying, organizing, and carrying forward the learning of each pattern from test chip designs to first product and then to multiple product variants. This learning includes results from printability simulation, defect scans and physical failure analysis, which are important for accelerating yield ramp.

Using pattern classification technology and a relational database, GLOBALFOUNDRIES has constructed a pattern database (PDB) of more than one million potential yield detractor patterns. In PDB, 2D geometries are clustered based on similarity criteria, such as radius and edge tolerance. Each cluster is assigned a representative pattern and a unique identifier (ID). This ID is then used as a persistent reference for linking together information such as the failure mechanism of the patterns, the process condition where the pattern is likely to fail and the number of occurrences of the pattern in a design. Patterns and their associated information are used to populate DRC Plus pattern matching libraries for design-for-manufacturing (DFM) insertion into the design flow for auto-fixing and physical verification. Patterns are used in a production-ready yield learning methodology to identify and score critical hotspot patterns. Patterns are also used to select sites for process monitoring in the fab.

In this paper, we describe the design of PDB, the methodology for identifying and analyzing patterns across multiple design and technology cycles, and the use of PDB to accelerate manufacturing process learning. One such analysis tracks the life cycle of a pattern from the first time it appears as a potential yield detractor until it is either fixed in the manufacturing process or stops appearing in design due to DFM techniques such as DRC Plus. Another such analysis systematically aggregates the results of a pattern to highlight potential yield detractors for further manufacturing process improvement.

Proceedings Article | 28 March 2014 Paper

Systematic physical verification with topological patterns

Vito Dai, Ya-Chieh Lai, Frank Gennari, Edward Teoh, Luigi Capodieci

Proceedings Volume 9053, 905304 (2014) https://doi.org/10.1117/12.2046709

KEYWORDS: Raster graphics, Manufacturing, Metals, Electronic design automation, Profiling, Design for manufacturability, Design for manufacturing, Optical alignment, Multilayers, Databases

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Design rule checks (DRC) are the industry workhorse for constraining design to ensure both physical and electrical manufacturability. Where DRCs fail to fully capture the concept of manufacturability, pattern-based approaches, such as DRC Plus, fill the gap using a library of patterns to capture and identify problematic 2D configurations. Today, both a DRC deck and a pattern matching deck may be found in advanced node process development kits. Major electronic design automation (EDA) vendors offer both DRC and pattern matching solutions for physical verification; in fact, both are frequently integrated into the same physical verification tool.

In physical verification, DRCs represent dimensional constraints relating directly to process limitations. On the other hand, patterns represent the 2D placement of surrounding geometries that can introduce systematic process effects. It is possible to combine both DRCs and patterns in a single topological pattern representation. A topological pattern has two separate components: a bitmap representing the placement and alignment of polygon edges, and a vector of dimensional constraints. The topological pattern is unique and unambiguous; there is no code to write, and no two different ways to represent the same physical structure. Furthermore, markers aligned to the pattern can be generated to designate specific layout optimizations for improving manufacturability.

In this paper, we describe how to do systematic physical verification with just topological patterns. Common mappings between traditional design rules and topological pattern rules are presented. We describe techniques that can be used during the development of a topological rule deck such as: taking constraints defined on one rule, and systematically projecting it onto other related rules; systematically separating a single rule into two or more rules, when the single rule is not sufficient to capture manufacturability constraints; creating test layout which represents the corners of what is allowed, or not allowed by a rule; improving manufacturability by systematically changing certain patterns; and quantifying how a design uses design rules. Performance of topological pattern search is demonstrated to be production full-chip capable.

Proceedings Article | 15 March 2012 Paper

Electrical design for manufacturability and lithography and stress variability hotspot detection flows at 28nmn

Philippe Hurat, Jianhao Zhu, Edward Teoh

Proceedings Volume 8327, 832715 (2012) https://doi.org/10.1117/12.916742

KEYWORDS: Lithography, Simulation of CCA and DLA aggregates, Laser Doppler velocimetry, Design for manufacturability, Transistors, Silicon, Standards development, Design for manufacturing, Instrument modeling, Current controlled current source

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