This paper shows the capability of chromeless phase lithography (CPL) and is particularly focused on different strategies for optical proximity corrections (OPC). A chromeless phase database is easily obtained from the original layout by changing the chromium pattern into a phase pattern. However, a specific optical proximity correction has to be applied due to the phase effect and the high transmission of the mask. Mask Error Enhancement Factor (MEEF) and process window for CPL technology have been estimated through wafer exposures. Moreover, various optical proximity correction strategies have been explored through a comparison between phase and chromium features such as hammerhead, zebra and scattering bars 1,2. Indeed, depending on the density of the pattern, we can improve the contrast and the process window by changing the local transmission. The transmission can be controlled by the addition of sub resolution chromium feature such as zebra chromium transverse features on the line for dense pattern, or chromium scattering bars in the space for a sparse pattern, or chromium patches on the line end. From 65 nm node measurements and 45 nm node simulations, the authors will then present the most effective sub resolution pattern to implement.
The merits of complementary double dipole illumination using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is investigated. Off-axis dipole illumination shows a significant improvement in the resolution for lines and spaces oriented along the direction perpendicular to the dipole orientation. However, there is also a significant loss of resolution along the dipole direction. Consequently, two dimensional circuit patterning requires a double exposure to improve the resolution in both directions. Thus, the original layout must be decomposed into two masks: one containing the features to be primarily imaged with one dipole and another one with features to be imaged in the complementary direction. The horizontal and vertical lines must be selected and protective patches are required on each mask to protect the pattern formed by the complementary exposure. The potential capability of the dipole illumination used in conjunction with the immersion lithography for 45 nm and 32 nm nodes will be described. The Mentor Graphic approach based on the model assisted decomposition for the Double Dipole Lithography (DDL) was applied to the small clips of the 2D layout of the gate level for random logic. The lithographic process window and the CD control will be estimated through simulation.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
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