In this paper we introduce new source-mask co-optimization (SMO) capabilities for EUV with specific support of the details of imaging with NXE:33×0 scanners. New algorithms have been developed that fully exploit the adjustability of the light distribution inside the NXE:33×0 flexible illuminator, FlexPupil. The fast NXE M3D+ model accurately predicts the reflective 3D mask effects and enables novel pupil symmetries and mask defocus optimization. This mitigates the H-V bias, Bossung tilt, and pattern shift caused by shadowing and non-telecentricity, and reduces the sensitivity to flare. New pupil optimization flows will be shown. The optimized pupils are fully compliant with NXE:33×0 scanner specifications. We will demonstrate enhanced imaging performance of this NXE specific SMO on 7 nm node logic cut masks and show benefits up to 20% improved CD uniformity, and a reduction in the maximum pattern shifts.
KEYWORDS: 3D modeling, Calibration, Data modeling, Photomasks, Lithography, Semiconducting wafers, Scanning electron microscopy, Atomic force microscopy, Process control, Etching
The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.
In this paper we will present ASML's holistic approach to lithography for EUV. This total approach combines the
various components needed to achieve the correct on-product demands of our customers in terms of patterning fidelity
across the entire image field and across the entire wafer.
We will start giving a general update on ASML's NXE scanner platform of which the 6th NXE:3100 systems is now
being shipped to a leading chipmaker. The emphasis will be on wafer imaging results for various applications such as
flash memory and logic's SRAM. Then we will describe the second holistic component, NXE-computational
lithography, which was developed to speed-up early learning on EUV and to achieve high accuracy on the wafers.
Thirdly, the YieldStar angular-resolved scatterometry tool that supports the scanner's stability was used to characterize
the system and calibrate the models.
The wafer-results reveal in detail predicted imaging effects of NXE lithography and allow a calibration of system
parameters and characterization of hardware components. We will demonstrate mask-induced imaging effects and
propose an improvement of the current EUV blank or mask-making processes.
EUVL requires the use of reflective optics including a reflective mask. The mask consists of an absorber layer pattern on
top of a reflecting multilayer, tuned for 13.53 nm. The EUVL mask is a complex optical element with many parameters
contributing the final wafer image quality. Specifically, the oblique incidence of light, in combination with the small
ratio of wavelength to mask topography, causes a number of effects which are unique to EUV, such as an HV CD offset.
These so-called shadowing effects can be corrected by means of OPC, but also need to be considered in the mask stack
design.
In this paper we will present an overview of the mask contributors to imaging performance at the 27 nm node and below,
such as CD uniformity, multilayer and absorber stack composition, thickness and reflectivity. We will consider basic
OPC and resulting MEEF and contrast. These parameters will be reviewed in the context of real-life scanner parameters
both for the NXE:3100 and NXE:3300 system configurations.
The predictions will be compared to exposure results on NXE:3100 tools, with NA=0.25 for different masks. Using this
comparison we will extrapolate the predictions to NXE:3300, with NA=0.33.
Based on the lithographic investigation, expected requirements for EUV mask parameters will be proposed for 22 nm
node EUV lithography, to provide guidance for mask manufacturers to support the introduction of EUV High Volume
Manufacturing.
Automatic layout optimization is becoming an important component of the DfM work flow, as the number of
recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly
difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM
improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer
optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics,
while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained
intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base
Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements
(CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler
was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM
checking and by wafer yields.
In this paper we present the method that NuFlare photomask inspection systems can use to strongly reduce
pseudo detections by use of TK-CMI software. The NuFlare inspection system is capable to detect the
smallest defects in the 45 and 32-nm nodes and has recently been introduced to production. It links up with
a compute cluster with Takumi's Criticality-Marker Information software (TK-CMI). TK-CMI quickly analyzes
the ~200GB post-OPC layout or multi-layer pre-OPC layout and assigns various types of criticality regions.
The basic set of criticalities is made to address the challenges that typical maskmakers experience. The TKCMI
system also supports design-intent-based criticalities. The NuFlare inspection system uses this full-mask
criticality information and generates flexible inspection recipes that inspect low-criticality areas with relaxed
sensitivity resulting in reduction of pseudo detections in such regions.
An automatic system that combines actions in both the image domain as well as in the layout-database domain for
accurate mask-defect analysis and application of design criticality will be presented. In this paper we will emphasize the
qualification and calibration of the system and its various pieces of functionality with the use of programmed defect
masks and low-voltage mask CD-SEM measurement data. Results on 1D and 2D programmed defects of various natures
are reported in dense layout as well as in real memory design layout. The results show that the system can accurately
extract mask CD-errors and defect sizes at a resolution far below that of the pixel-size of state-of-the-art mask-defect
inspection tools at nanometer resolution.
We will further demonstrate that mask-defect-inspection data can contain optical anomalies when defect or residual
feature sizes are smaller than the inspection wavelength. Mask inspection images then no longer show the real defect.
These anomalies can be analyzed with the system using advanced image actions.
Finally, we will demonstrate the capability to calculate the effects that defects have on final wafer printability even
without the need for input layout. Hence, model-based defect properties can be combined with rule-based defect
properties as well as multi-layer, design-based criticality-region properties for utter flexibility in defect disposition
capability.
DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product
designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful,
these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With
these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long
and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness.
An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM
optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM
model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and
silicon experiment results will be presented.
We present a novel software system that combines design intent as known by EDA designers with defect inspection
results from the maskshop to analyze the severity of defects on photomasks. The software -named Takumi Design-
Driven Defect Analyzer (TK-D3A)- analyzes defects by combining actions in the image domain with actions in the
design domain and outputs amongst others flexible mask-repair decisions in production formats used by the maskshop.
Furthermore, TK-D3A outputs clips of layout (GDS/OASIS) that can be viewed with its graphical user interface for easy
review of the defects and associated repair decisions. As inputs the system uses reticle defect-inspection data (text and
images) and the respective multi-layer design layouts with the definitions of criticalities.
The system does not require confidential design data from IDM, Fabless Design House, or Foundry to be sent to the
maskshop and it also has minimal impact on the maskshop's mode of operation. The output of TK-D3A is designed to
realize value to the maskshop and its customers in the forms of: 1) improved yield, 2) reduction of delivery times of
masks to customers, and 3) enhanced utilization of the maskshop's installed tool base.
The system was qualified together with a major IDM on a large set of production reticles in the 90 and beyond-65 nm
technology nodes of which results will be presented that show the benefits for maskmaking. The accuracy in detecting
defects is extremely high. We show the system's capability to analyze defects well below the pixel resolution of all
inspection tools used, as well as the capability to extract multiple types of transmission defects. All of these defects are
analyzed design-criticality-aware by TK-D3A, resulting in a large fraction of defects that do not need to be repaired
because they are located in non-critical or less-critical parts of the layout, or, more importantly, turn out to be repairable
or negligible despite of originally being classified as unrepairable when no such criticality knowledge is used. Finally,
we show that the runtimes of TK-D3A are relatively short, despite the fact that the system operates on full-chip designs.
Preserving the accuracy of pattern reproduction on silicon with the decreasing linewidth usually requires paying increasingly higher prices for the masks. However, the advances in optical, device and circuit simulation tools are offering interesting alternatives to the tightening of reticle specifications. The performance of the next generation circuits can be verified by integrated simulation at the mask, device, and cell level. The tradeoff between mask quality, process options, product characteristics, and manufacturing cost can be thereby analyzed. Such integrated simulation impacts also mask shop and process deliverables. As an example, it was shown the potential to reduce reticle rejection rate by several times. In this work, integrated simulation helped choose the most economical option for the poly mask process, to control channel CD variation related to the discontinuity of gate pattern in multi-transistor memory cells. We evaluated the tradeoff between cell performance and the cost of the phase shift mask set to reduce poly CD variation. Based on the cell stability dependence on photo process parameters, we proved that the low cost approach can still yield economically satisfactory results.
We selected alternating phase shift technology to image 90nm dense lines with a pitch of 200nm for volume production purposes. We simulated which settings of illumination were needed to achieve these pitches taking into account the boundary condition of the exposure tool with the wavelength of 248nm and its maximum NA of 0.68. The simulations showed, that normalized image log slope (NILS) is above 2 for a focus range of at least 600nm, if an alternating phase shift mask is used at the very low σ of 0.2 Typical manufacturing conditions with process variations, lens errors and mask deviations were included in the simulations. Based on these results, on the one hand the mask was specified and manufactured; on the other hand the tool was adaptated to the low σ requirement and the specific lens error sensitivities. Shipley's UV212 on BARC AR7 was used at a resist thickness of 250nm. The resist process was optimized by reducing the concentration of the developer. Finally, experimental verification of this entire system with wafer exposures shows that 90nm lines with a pitch of 200nm could be printed with a focus window of more than 600nm.
We present design-for-manufacturing and yield (DfM/DfY) results on SRAM of the 65-nm node by connecting knowledge of device performance with that of lithographic optical enhancement techniques. Of special interest was the lithographic quality of line-ends and gates, the former being the most critical for yield and manufacturing control. Scalability towards lower technology nodes was also part of the choice. All these considerations led to the choice of alternating-aperture phase-shift lithography as optimal reticle-enhancement technique. Predictions from simulations were verified on the wafer for SRAM cells of multiple geometry contexts, misalignment was included, and the illuminator was optimized.
A new methodology for completely phase-shifting a poly layout without creating local phase conflicts was proposed for lithographic techniques combining one phase-shifting mask and one binary mask exposure1. Critical and non-critical areas of the layout are identified and phase conflicts are avoided by splitting the shifter regions from non-critical areas to non-critical areas without crossing critical areas. The out-of-phase splits of the shifter regions are removed using the binary exposure.
Simulation results and experimental data collected for 90nm technology node show no sign of process latitude loss around the areas where the shifters are split. The overlay latitude is commensurate with 90nm technology scanner requirements (tool to itself). Simulation work shows that the two exposures are balancing each other out of focus in the 45-degree cut regions thus ensuring large focus latitude. The focus latitude reported is larger than the main feature process latitude; this result was confirmed experimentally. A set of phase-shifting design rules commensurate with an aggressive 65nm node technology (140nm pitch) was put together. Under these conditions, we have identified certain types of cuts that should be avoided during the generation of the phase-shifting layout; this is primarily the case for cuts in “elbow” structures which exhibit limited process latitude. Other cuts like line-end cuts will have to be modified. In this case we have proposed a side cut when the line-end is facing a perpendicular line with a minimum spacing. Despite these restrictions, test structures for the 65nm technology node were successfully converted with no phase conflicts. Experimental verification done on test structures using a 0.75 NA, 193nm scanner demonstrates 0.33 k1 capability using the full phase methodology.
Experimental lithographic data are presented that show that ArF can comfortably be extended to the 65-nm node. All features in the designs were patterned with alternating phase-shift lithography according to the Full-Phase methodology without any form of optical proximity corrections. Process windows through-pitch, latitude trade-off curves, CD uniformity and pitch linearity are presented. Furthermore, the emphasis is on 2-dimensional design performance for 60, 70 and 80-nm node designs at k1 values as low as 0.28. The current ArF infrastructure for mask making, step-and-scan systems, and resist technology was used for this.
The latest generations of CMOS are being patterned at decreasing k1 values, which is one of the reasons that their process windows are decreasing. Hence, control of the process gets more and more important and in-die critical dimension (CD) measurements are gradually being introduced for the monitoring of the in-line lithographic process performance. Because an increasingly large portion of the CD-error-budget is already being consumed by the mask-making, there is also a strong tendency toward improving process control of the mask, which in turn leads to a rapid increase in the number of mask-CD measurements even within the die. The main two reasons for the larger contribution of the mask to the error budget at wafer level are: 1) the mask process itself, and 2) the mask-error enhancement factor (MEEF), the magnification factor of reticle-to-wafer error. The latter factor and its lithographic process dependence are very much depending on the shape of a feature and its local vicinity. For example a narrow dense binary line has a larger MEEF than an isolated line and its partial derivative to defocus is much larger. Hence it would make sense to relate such MEEF process-behaviour to the 2D layout shapes in the design and use that as a metric during mask qualification. In this work the Silicon-versus-layout verification (SiVL) tool- inherently an OPC evaluation tool- is used to find such features in the layout that will be most critical for the wafer lithographic process by automatic extraction and selection of their MEEF values. This information can then be used to generate realistic mask specifications and forms a cost-method to control both mask quality and price.
During the development of process generations with critical dimensions (CDs) around or even far below the wavelength used for printing, the wafer exposure step has become more and more complicated due to the non-linearities that occur within this sub-wavelength regime. These non-linearities give rise to a variety of optical-proximity effects (OPE) that must then be corrected for (optical-proximity correction, OPC).
At the same time, the reticle errors are consuming a larger part of the total error budget on the wafer than we have seen in the past. As a consequence, detailed assessments of the reticle quality are gaining more importance and the average number of measurements for qualification of a high-end reticle is rapidly increasing. Within-die CD measurements are becoming common practice for such reticles. Quite often these measurement points are selected randomly. However, regions within the design with relatively low aerial-image contrast during imaging will be subject to the largest amplification of the mask-errors (highest Mask-Error-Enhancement Factor, MEEF).
In this work a solution is presented in which measurement points with high MEEF-values can be selected from any given layout data. The method is embedded into the standard mask data preparation flow using CATS. Focus is on the automation necessary to generate set-up files for CD metrology tools, such as the Leica-MueTec M5k. The methodology has been applied in a CMOS volume production site.
We report results from fast aerial-image simulations of defects with variable transmission and residual phase (which we call soft or phase defects in this work) in 193-nm lithography for the 100-nm node. These results include a qualitative benchmarking of mask-types and their sensitivity to defects with variable transmission and residual phase. We treat the cases of soft (phase) defects on (1) binary masks, (2) binary masks with assist-bars, (3) bright-field attenuated phase-shift masks, (4) bright-field attenuated phase-shift masks with assist-bars, and (5) alternating phase-shift masks. The focus of this paper is to study deviations of critical features close to such defects, thereby limiting the discussion to isolated lines. The various optical enhancement techniques show striking differences in their sensitivity to defects, which may lead to differences in repair criteria for mask making. Furthermore, we show that the distance between critical feature and defect is a critical parameter and that differences in aspect ratio of the defects studied here have a negligible effect on the critical feature.
The main advantage of the double-exposure, alternating-aperture phase-shifting mask (AltPSM) technique is that a critical mask layer (e.g. poly gate) can be separated into two regions and the lithographic processes optimized for each separately. The most critical regions, the gates, are usually patterned by a dark-field AltPSM, as it provides the best patterning performance and CD-control for isolated and semi-dense gates. The less critical binary intensity mask defines the local interconnect lines and gate trim-out regions. However, as the technology rapidly moves into the sub-100 nm node and beyond, the local interconnects become critical as well. The binary trim mask will also need other resolution enhancement techniques (RET). RETs such as off-axis illumination (annular or quadrupole), in combination with optical proximity corrections (OPC), are required in order to improve process windows and CD-control on the interconnecting poly layer. These two masks require quite different lithography settings to achieve the optimum process performance for the 100-nm node. For example, while the AltPSM exposure will perform best under moderate or high numerical aperture (NA) and relatively low partial coherence, the trim mask patterning requires higher NA and higher partial coherence to resolve the 240nm pitches. At the same time, both masks show different optical proximity effects (OPE), which will require additional process optimization and correction by concurrently distributing OPC on the shifter and trim masks. In this paper, we present a full CMOS process optimization including illumination mode and proximity correction for both poly-layer images for the (sub-) 100nm node, using 193-nm lithography.
Today some IC manufacturers obtain finer circuit geometries by adding scatter bars (SB) to conventional binary masks as an efficient resolution enhancement technique (RET).1 These SB perform best when they are wide. However, to achieve better resolution and wider process windows modern stepper equipments feature lower wavelengths and higher numerical aperture lenses. These new steppers require narrower scatter bars to prevent them from printing on the wafer, and their effectiveness as a RET is diminishing as we follow the stepper technology 'roadmap'.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.