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PSCAR utilizes an area-selective photosensitization mechanism to generate more acid in the exposed areas during a UV exposure. PSCAR is an attempt to break the resolution, line-edge-roughness, and sensitivity trade-off (RLS trade-off) relationships that limit standard chemically amplified resists. The photosensitizer, which is generated in exposed area by a photoacid catalytic reaction, absorbs the UV exposure light selectively and generates additional acid in the exposed area only.
Material development and UV exposure uniformity are the key elements of PSCAR technology for semiconductor mass fabrication. This paper will review the approaches toward improvement of PSCAR resist process robustness. The chemistry’s EUV exposure cycle of learning results from experiments at imec will be discussed.
To be effective during the lithographic EUV material screening phase for such tight pitches, it is necessary to implement complementary metrology analyses that can provide precise information on the resist roughness and a quick feedback on the quantification of nano-failures (nano-bridges, broken lines, merging or missing contacts) induced by a stochastic EUV patterning regime, the random nature of the light-matter interaction and consequent chemical reactions. Beside the traditional approach to characterize a resist with metrics as exposure latitude (EL%), depth of focus (DoF) and line-edge-roughness (LER) based on CDSEM measurements, we have used the power spectra density (PSD) [4] to get an unbiased value of the resist line roughness (LWR and LER) by using Fractilia metroLERTM commercial software. Further, we have used Stochalis imec software [5] to quantify patterning nano failures providing an early stage assessment on the patterning fidelity of the examined resists.
We present the resist characterization results for 32nm dense line-space pattern on different substrates and for 36nm dense and orthogonal contact hole pitch pattern for different photoresists. Two positive tone chemically amplified (CA) resists have been identified at the exposure dose of 45mJ/cm2 and 33mJ/cm2 for logic (pitch 32nm dense line/space) and memory (pitch 36nm dense contact holes) use cases, respectively.
We present the lithography performance of the MTR1 resist series in two formulations – a high-speed baseline, and a formulation designed to enhance the multi-trigger behaviour. Additionally, we present results for the MTR2 resist series, which has been designed for lower line edge roughness. The high-speed baseline resist (MTR1), showed 18 nm resolution at 20mJ/cm2. The MTR2 resist shows 16nm half pitch lines patterned with a dose of 38mJ/cm2, giving a LER of 3.7 nm. Performance across multiple process conditions are discussed. We performed etch rate measurement and the multi-trigger resist showed etch resistance equivalent or better than standard chemically amplified resist. This could compensate for the lower film thickness required to avoid pattern collapse at pitch 32nm.
Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced.
For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.
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