Proceedings Article | 2 April 2010
KEYWORDS: Transistors, Line width roughness, Line edge roughness, Computer aided design, Cadmium sulfide, Optical proximity correction, Semiconducting wafers, Front end of line, Metrology, OLE for process control
LER and LWR have long been considered a primary issue in process development and monitoring.
Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device.
Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end
layers. Traditionally as can be seen in many publications, for the front end of line the focus is mainly on Poly and
Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed.
Following our research done on sources of gate leakage, we found leakage current (Ioff) in some processes to be
highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore
we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout
and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local
Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment
around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly
spacer's roughness.
A dedicated test chip was designed for the experiments, having various transistors layout configurations with
different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative
algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges
and from other spaces.
To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD.
On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their
morphology is different compared with Photo/Etch traditional structures , and dimensions vary significantly.
In this paper we present metrology and characterization of poly spacer LLWR and LLER compared to that of the
poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture
(final layout, including OPC). We will show how the spacer deposition may reduce, keep or even enlarge the roughness
measured on Poly, depending on transistor layout , but surprisingly, not dependent on proximity effects.
