This work presents a fixed point simulation of Compressed Sensing (CS) and reconstruction for Super-Resolution task using Image System Engineering Toolbox (ISET). This work shows that performance of CS for super- resolution in fixed point implementation is similar to floating point implementation and there is negligible loss in reconstruction quality. It also shows that CS Super-Resolution requires much less computation effort compared to CS using Gaussian Random matrices. Additionally, it also studies the effect of Analog-to-Digital-Converter (ADC) bitwidth and image sensor noise on reconstruction performance. CS super-resolution cuts the raw data bits generated from image sensor by more than half and conversion of reconstruction algorithm to fixed point allows one to simplify the hardware implementation by replacing expensive floating point computational units with faster and energy efficient fixed point units.
This paper performs Compressed Sensing (CS) super-resolution for images sampled using pixel binning. It extends Image Sensor Engineering Toolbox (ISET) to accurately simulate the CS acquisition and reconstruction process. Using ISET allows designers to easily explore large design space and measure the performance of CS under different conditions such as lighting, noise etc. without going through the cycle of full system development. CS using binning can make CS programmable and reduce power consumed in image acquisition process by half while maintaining good reconstruction quality. This work shows the results of CS reconstruction with different sensor noise and lighting conditions. It shows that even at low Peak Signal to Noise Ratio (PSNR) of approximately 26 dB and Structural Similarity (SSIM) index of .7, the perceptual quality of image is quite good.
This paper presents a methodology for programmable on-sensor compressed sensing (CS) of images using pixel binning techniques. This work uses simple sparse deterministic matrices for the ease of implementation. The use of binning technique allows pixels to shift between CS and non-CS modes by the use of control signals. It also allows flexibility to perform CS on selected regions of image. Operation on CS mode has potential to cut raw data rate and power consumption by more than half, double the frame rate and increase low light sensitivity while achieving reconstruction PSNR close to 34 dB. This work also shows that CS has a very good potential for reconstruction of binned images.
Advances in CMOS technology have made high-resolution image sensors possible. These image sensors pose significant challenges in terms of the amount of raw data generated, energy efficiency, and frame rate. This paper presents a design methodology for an imaging system and a simplified image sensor pixel design to be used in the system so that the compressed sensing (CS) technique can be implemented easily at the sensor level. This results in significant energy savings as it not only cuts the raw data rate but also reduces transistor count per pixel; decreases pixel size; increases fill factor; simplifies analog-to-digital converter, JPEG encoder, and JPEG decoder design; decreases wiring; and reduces the decoder size by half. Thus, CS has the potential to increase the resolution of image sensors for a given technology and die size while significantly decreasing the power consumption and design complexity. We show that it has potential to reduce power consumption by about 23% to 65%.
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