As wafer manufacturing shrinks size and pitch of features, and EUV lithography introduces high NA, the control of photomask pattern placement error that contributes to wafer overlay becomes a critical requirement for leading-edge devices. For sub-3nm node devices, the pattern complexity has increased and the exposure dose has also risen due to the use of low-sensitivity resist. Accordingly, to improve the pattern fidelity and reduce the exposure time, masks are manufactured using Multi-Beam Mask Writer (MBMW). As a result of analyzing the mask pattern placement error budget for the main EUV resist of sub-3nm node device, e-beam resist charging was found to be the most significant factor. This is primarily due to the inability to use a charging dissipation layer (CDL), caused by defect issues and degradation of critical dimension (CD) linearity. In this paper, we conduct an in-depth analysis of mask pattern placement errors induced by the charging effect in the MBMW and present a charging control methodology to mitigate these pattern-density-dependent errors. We test the charging effect reduction, an integrated solution of hardware and software for charging control in the MBMW, and showcase its performance for two resists. When applied to mass productions, the charging effect correction (CEC) significantly reduces mask pattern placement errors in a single cell and improves mask overlay between two critical layers aligned in an overlay alignment scheme. Ultimately, this leads to a reduction of wafer in-field overlay error.
Multibeam mask writers(MBMW) have been rapidly occupying on the field of leading edge EUV mask patterning for last several years. Thanks to outstanding ability of MBMW characteristics, sophisticated mask patterns and higher local pattern fidelity with low sensitivity E-beam resist can be realized in EUV era. Now most mask makers want to make good use of MBMW as a standard of making high-end grade masks such as Memory, Logic chips and etc. For this reason, they require higher pattern accuracy, faster writing time, higher data handling efficiency and matured machine stability aiming for the innovative mask making environment. Moreover, Larger coverage is needed as well not only for Low/High-NA EUV masks but also for even ARF masks.
In this paper, we touch key items with regard to comprehensive requirements from the mass production's point of view, for the versatile machines, several works and challenges to overcome on MBMW will be discussed.
With the introduction of the multi-beam mask writing (MBMW) technology, efficient processing and precise patterning of curvilinear mask shapes are becoming increasingly important due to the wafer lithography advantages associated with the shapes. However, as the complexity of the curvilinear mask shapes increases, it becomes difficult to precisely characterize the curvilinear mask shapes. Barrier to this is prediction and reflection of the nature of curvilinear mask shapes. Therefore, in the industry, a novel algorithm method for accurate patterning is a major concern. In this study, we discuss the status of curvilinear mask shapes and patterning technology. By adopting machine learning, we develop a novel algorithm with considering the nature of curvilinear mask shapes. To evaluate practical use and accuracy of model, we demonstrate that the algorithm has significant value to guarantee the mask critical dimension (CD).
An extreme ultraviolet (EUV) pellicle is employed to prevent contamination on a EUV mask. The EUV pellicle, a high-priced membrane, gets contaminated during both the fabrication process and exposure. The lifetime of the pellicle can be extended by the removal of these contaminants. In this study, a particle removal technique for the EUV pellicle was developed. A functionalized atomic force microscopy (AFM) probe and programable particle contamination system were developed for particle removal and evaluation of the technique, respectively. The particle was removed with a pinpoint technique and the inherent vibration of the free-standing membrane was suppressed during the process. The process window of the proposed pinpoint cleaning technique was investigated to ensure damage-free particle removal and the nanomanipulated functionalized probe resulted in efficient particle removal from the pellicle surface without damage.
Semiconductor manufacturing industry has reduced the size of wafer for enhanced productivity and performance, and Extreme Ultraviolet (EUV) light source is considered as a promising solution for downsizing. A series of EUV lithography procedures contain complex photo-chemical reaction on photoresist, and it causes technical difficulties on constructing theoretical framework which facilitates rigorous investigation of underlying mechanism. Thus, we formulated finite difference method (FDM) model of post exposure bake (PEB) process on positive chemically amplified resist (CAR), and it involved acid diffusion coupled-deprotection reaction. The model is based on Fick’s second law and first-order chemical reaction rate law for diffusion and deprotection, respectively. Two kinetic parameters, diffusion coefficient of acid and rate constant of deprotection, which were obtained by experiment and atomic scale simulation were applied to the model. As a result, we obtained time evolutional protecting ratio of each functional group in resist monomer which can be used to predict resulting polymer morphology after overall chemical reactions. This achievement will be the cornerstone of multiscale modeling which provides fundamental understanding on important factors for EUV performance and rational design of the next-generation photoresist.
Currently, we are supplying defect-free EUV mask for device development. This was one of the biggest challenges in the implementation of EUV lithography for high volume manufacturing (HVM). It became possible to hide all multi-layer defects by using defect avoidance technique through improvement of blank mask defectivity and development of actinic blank inspection tool. In addition, EUV pellicle is also considered as a requisite to guarantee predictable yield. Both development of mask shop tools and preparation of EUV scanner for pellicle are going well. However, still membrane needs to be much improved in terms of transmittance and robustness for HVM. At the conference, EUV mask readiness for HVM will be discussed including blank defect improvement, preparation of actinic tools and pellicle development.
We introduce an extreme ultraviolet lithography (EUVL) mask defect review system (EMDRS) which has been developing in SAMUSNG. It applies a stand-alone high harmonic generation (HHG) EUV source as well as simple EUV optics consisting of a folding mirror and a zoneplate. The EMDRS has been continuously updated and utilized for various applications regarding defect printability in EUVL. One of the main roles of the EMDRS is to verify either mask repair or mask defect avoidance (MDA) by actinic reviews of defect images before and after the process. Using the MDA, small phase defects could be hidden below absorber patterns, but it is very challenging in case of layouts with high density patterns. The EMDRS clearly verify the success of the MDA while conventional SEM could not detect the images. In addition, we emulate images of the sub-resolution assist features (SRAFs) by the EMDRS and compared them with the wafer exposure results.
For decades, downsizing has been a key issue for high performance and low cost of semiconductor, and extreme ultraviolet lithography is one of the promising candidates to achieve the goal. As a predominant process in extreme ultraviolet lithography on determining resolution and sensitivity, post exposure bake has been mainly studied by experimental groups, but development of its photoresist is at the breaking point because of the lack of unveiled mechanism during the process. Herein, we provide theoretical approach to investigate underlying mechanism on the post exposure bake process in chemically amplified resist, and it covers three important reactions during the process: acid generation by photo-acid generator dissociation, acid diffusion, and deprotection. Density functional theory calculation (quantum mechanical simulation) was conducted to quantitatively predict activation energy and probability of the chemical reactions, and they were applied to molecular dynamics simulation for constructing reliable computational model. Then, overall chemical reactions were simulated in the molecular dynamics unit cell, and final configuration of the photoresist was used to predict the line edge roughness. The presented multiscale model unifies the phenomena of both quantum and atomic scales during the post exposure bake process, and it will be helpful to understand critical factors affecting the performance of the resulting photoresist and design the next-generation material.
Extreme ultraviolet (EUV) lithography has received much attention in the semiconductor industry as a promising candidate to extend dimensional scaling beyond 10nm. Recently EUV pellicle introduction is required to improve particle level inside scanner for EUV mass production. We demonstrate that a new pellicle material, nanometer-thick graphite film (NGF), is one of the best candidates of EUV pellicle membrane. A NGF pellicle with excellent thermal (ε≥0.4 @R.T, <100nm), mechanical (415MPa @~100nm), chemical and optical (24hrs durability under exposure of EUV/H2 at 4W/cm2 with pH2~5Pa) properties can be a promising and superb candidate for EUV pellicle membrane compared to Si pellicles with capping layers.
A new PSM using high transmittance is developed to overcome patterning process limits in ArF immersion lithography. We optimized mask structure, materials, and film thicknesses for patterning process. A new material for phase-shifter is applied to the HT-PSM to exhibit higher transmittance in ArF wavelengths and the thickness of the new material is thinner than that of the conventional 6% phase-shifter (MoSiON). A new blank structure using a MoSi shading layer with double Cr hardmasks (HM) is developed and suggested for the HTPSM process. Double HM blank stacks enable the HT-PSM to adopt thin PR process for resolution enhancement in mask process. The first Cr on the MoSi is utilized as a HM to etch MoSi shading layer, an adhesion layer for PR process, and also a capping layer to protect blind area during MoSi and phase-shifter etching. In contrast, the role of the second Cr between MoSi and phase-shifter is an etch stopper for MoSi and a HM to etch phase-shifter at the same time. However, Double HM process has some problems, such as first Cr removal during second Cr etching and complex process steps. To solve the Cr removal issues, we evaluated various Cr layers which have different etchrates and compositions. According to the evaluations, we optimized thicknesses and compositions of the two Cr layers and corresponding etching conditions. Lithography simulations demonstrate that the new HT-PSM has advantages in NILS in aerial images. As a result, initial wafer exposure experiments using the HT-PSM show 13-32% improvements in LCDU compared to that of the conventional 6% PSM due to its higher NILS.
Masks used for sub-20 nm half pitch of devices are required to be defect-free as well as to have more
complicate and smaller patterns. For higher resolution for sub-20 nm device, the masks that can provide wider process
windows on wafers are made using new e-beam resists and new mask materials. An introduction of advanced mask
systems needs methodologies to overcome defect challenges that did not occur at previous mask systems. The defects
should be related with chemical and physical properties from negative and positive e-beam resists or/and new type
blanks used for advanced masks such as EUV or optical masks. As a mask pattern size is shrunken, the masks also have
complicate structures and different surface properties from low end mask systems. Defect removal on the masks is
important even at a develop process among mask manufacturing processes. This paper reports that advanced technology
applications on mask develop processes have been performed to remove defects on the masks. First, a new rinse system
has applied into a mask develop process for defect reduction. Second, a new develop process was also performed to
remove defects on masks. The new develop process combined with the new rinse system has reduced more than 50% of
defects including e-beam resist residue defects and other defects. This paper mainly focuses on defects related to
negative and positive resists on masks and their solutions to reduce or/and remove the defects, which are used for sub-20
nm half pitch of devices, in terms of mask develop process.
KEYWORDS: Lithography, Zirconium, Atomic force microscopy, Metals, Coating, Image processing, Electron beam lithography, Oxides, Atomic force microscope, Line edge roughness
New inorganic resist materials based on metal complexes were investigated for atomic force microscope (AFM)
lithography. Phosphoric acids are good for self-assembly because of their strong binding energy. In this work, zirconium
phosphonate system are newly synthesized for spin-coatable materials in aqueous solutions and leads to negative tone
pattern for improving line edge roughness. Low electron exposure by AFM lithography could generate a pattern by
electrochemical reaction and cross-linking of metal-oxo complexes. It has been reported that the minimum pattern results
are affected by lithographic speed, and the applied voltage between a tip and a substrate.
A thin silicon oxy-nitride hard mask on the PSM blank is needed for the feature patterning with the size smaller
than 70 nm. It is a good material for hard mask. However, the electrical property of silicon oxy-nitride with the thickness
smaller than 10 nm causes the chromium surface damage during the mask processes. From the measurement of the
surface damage, we figure out that the chromium surface damage is originated from the charging and the dielectric
breakdown phenomena. In our present work, two types of silicon oxy-nitride film with the thicknesses of 5 nm and 12
nm are tested for verifying optimal mask fabrication processes. We find that the occurrence of ESD damage is related to
the thickness of silicon oxy-nitride hard mask and mask fabrication process conditions. The optimal fabrication process
condition for silicon oxy-nitride thin film hard mask, in which break-down never occurs, is discussed.
EUV lithography has been investigated as one of the next generation lithography technologies for sub-20 nm patterning because of its high resolution capability. However, outgassing from EUV resists should be improved in order to prevent optic contamination and to implement EUV lithography for high-volume manufacturing. Recently, in e-beam lithography for fabrication of photomask, the resist related outgassing has been also considered as one of the critical issues like that of EUV resists. E-beam exposure dose has been increased gradually in order to make fine patterns with better resolution and line edge roughness. As a result, the total resist outgassing in the application of lower sensitive resists could be increased due to longer exposure time in high vacuum and higher amount of organic compounds such as a photoacid generator and a quencher during e-beam irradiation. Therefore, the study of e-beam resist outgassing needs to understand correlations between outgassed chemical components from resists and e-beam optic contamination. The outgassing evaluations of current three kinds of positive e-beam resists were performed by using a EUV outgassing machine. The commercial e-beam resists show less contamination results compared to that of general EUV resists, relatively. However, the outgassing of e-beam resists was increased with decreasing resist sensitivity. In this view point, the outgassing should be considered as one of the important properties of the newly developed chemically amplified e-beam resists. Therefore, these e-beam resist outgassing results could be used as important data for development of next generation e-beam resists with lower sensitivity, to prevent the e-beam exposure equipment contamination.
As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement
is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error,
the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam
mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and
contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for
these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam
shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the
pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout.
And it affects the quality of CD and image placement too.
In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is
presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer.
From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and
beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for
various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam
writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing
conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is
studied for future e-beam mask writing for 22nm node and beyond.
By the development of double exposure technique and the EUV lithography the pattern placement error of photomask is
interested because of its impact on size and position of wafer pattern. Among various sources to induce the pattern
placement error, we have focused on the resist charging effect and shown that the resist charging effect generates pattern
position error and CD variation. Based on experiment and simulation, we present quantitatively the dependence of
position error on pattern density, pattern shape, and writing order. Furthermore, we have discussed the model to describe
the charging effect and its agreement with experiment, and correction method to remove the resist charging effect.
KEYWORDS: Photomasks, Extreme ultraviolet, Scattering, Monte Carlo methods, Ray tracing, Electron beam lithography, Molybdenum, Metals, Ion beams, Laser scattering
The ray tracing of electron based on Monte Carlo is simulated by GEANT software to investigate the electron scattering
property in ArF photomask and EUV photomask. By Monte Carlo simulation, we have presented the mechanism of
electron scattering in EUV photomask and simulated the electron distribution which gives rise to change the patterning
performance of EUV photomask, compared with those of ArF photomask. Furthermore, the overlay error of EUV
photomask has been analyzed by the charging model.
EUV photomask has the additional electron distribution in the range of 2um, which comes from the strong electron
scattering at Mo/Si multilayer. Because of this additional electron distribution, EUV photomask has the pattern size
error due to proximity effect of electron when the conventional Gaussian function is used to correct the proximity effect
of ArF photomask. The maximum residual error due to the proximity effect in EUV photomask is 7nm. Furthermore, we
have confirmed that the linearity of pattern size is so different from ArF photomask and it is well explained with the
Gaussian blur model based on the electron distribution of EUV photomask.
As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better
patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam
size and position accuracy for hp 32nm and beyond generation.
At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension
(CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view
point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm
because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern.
Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and
to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.
As semiconductor features shrink in size and pitch, the extreme control of CD uniformity and MTT is needed for
mask fabrication with e-beam lithography. And because of huge shot density of data, the writing time of e-beam
lithography for mask fabrication will be increased rapidly in future design node.
The beam drift caused by charging of optic system and current density drift can affect the beam size, position and
exposure dose stability. From the empirical data, those are the function of writing time. Although e-beam lithography
tool has the correction function which can be applied during writing, there are remained errors after correction which
result in CD uniformity error. According to the writing time increasing, the residual error of correction will be more
important and give the limit of CD uniformity and MTT.
In this study, we study the beam size and exposure dose error as a function of time. Those are mainly caused by
charging and current density drift. And we present the predicted writing time of e-beam lithography below 32nm node
and estimate its effect on CD control error. From the relation between writing time and CD control error, we achieve the
limit of CD uniformity with e-beam mask writer. And we suggest the method to achieve required CD uniformity at
22nm node and beyond.
As the design node gets smaller, using the aggressive mask optimization becomes indispensable emerging technology.
However, during the aggressive optimization, we have frequently met problems that the optimized feature size gets
smaller as Mask manufacturing Rule Checking (MRC) limitation. In this case, process window cannot improve more.
Moreover, mask drawing error could be significant when the optimized main feature is as small as MRC limitation. As a
solution for this problem, we have generally tried to develop the advanced mask manufacturing process. However,
nowadays, it is truly not easy to improve the mask resolution.
In this study, we found out the fact that the current MRC parameters are not good enough to reflect the mask patterning
limitation. Thus, many small patterns have been eliminated by the MRC during the optimization, even though the
patterns could be drawn well on the mask. In this paper, we suggest more effective MRC parameter; area based MRC.
We introduce the evaluation result that represents the actual coverage of MRC. It proves that the area based MRC can
reflect the mask process limitation much better than current MRC. Finally it is shown that the effect and utility of the
area based MRC on the practical case by using inverse lithography technology (ILT).
SRAF (sub-resolution assist feature) generation technology has been a popular resolution enhancement technique in
photo-lithography past sub-65nm node. It helps to increase the process window, and these are some times called
ILT(inverse lithography technology). Also, many studies have been presented on how to determine the best positions of
SRAFs, and optimize its size. According to these reports, the generation of SRAF can be formulated as a constrained
optimization problem. The constraints are the side lobe suppression and allowable minimum feature size or MRC (mask
manufacturing rule check). As we know, bigger SRAF gives better contribution to main feature but susceptible to SRAF
side lobe issue. Thus, we finally have no choice but to trade-off the advantages of the ideally optimized mask that
contains very complicated SRAF patterns to the layout that has been MRC imposed applied to it. The above dilemma can
be resolved by simultaneously using lower dose (high threshold) and cleaning up by smaller MRC. This solution makes
the room between threshold (side lobe limitation) and MRC constraint (minimum feature limitation) wider. In order to
use smaller MRC restriction without considering the mask writing and inspection issue, it is also appropriate to identify
the exact mask writing limitation and find the smart mask constraints that well reflect the mask manufacturability and the
e-beam lithography characteristics.
In this article, we discuss two main topics on mask optimizations with SRAF. The first topic is on the experimental work
to find what behavior of the mask writing ability is in term of several MRC parameters, and we propose more effective
MRC constraint for aggressive generation of SRAF. The next topic is on finding the optimum MRC condition in
practical case, 3X nm node DRAM contact layer. In fact, it is not easy to encompass the mask writing capability for very
complicate real SRAF pattern by using the current MRC constraint based on the only width and space restriction. The
test mask for this experimental work includes not only typical split patterns but also real device patterns that are
generated by in-house model-based assist feature generation tool. We analyzed the mask writing result for typical
patterns and compared the simulation result, and wafer result for real device patterns.
Lithographic process steps used in today's integrated circuit production require tight control of critical
dimensions (CD). With new design rules dropping to 32 nm and emerging double patterning processes,
parameters that were of secondary importance in previous technology generations have now become
determining for the overall CD budget in the wafer fab. One of these key parameters is the intra-field mask
CD uniformity (CDU) error, which is considered to consume an increasing portion of the overall CD
budget for IC fabrication process. Consequently, it has become necessary to monitor and characterize CDU
in both the maskshop and the wafer fab.
Here, we describe the introduction of a new application for CDU monitoring into the mask making process
at Samsung. The IntenCDTM application, developed by Applied Materials, is implemented on an aerial
mask inspection tool. It uses transmission inspection data, which contains information about CD variation
over the mask, to create a dense yet accurate CDU map of the whole mask. This CDU map is generated in
parallel to the normal defect inspection run, thus adding minimal overhead to the regular inspection time.
We present experimental data showing examples of mask induced CD variations from various sources such
as geometry, transmission and phase variations. We show how these small variations were captured by
IntenCDTM and demonstrate a high level of correlation between CD SEM analysis and IntenCDTM mapping
of mask CDU. Finally, we suggest a scheme for integrating the IntenCDTM application as part of mask
qualification procedure at maskshops.
As feature size continuously decreasing new techniques to improve quality of wafer are developed. Hence a lot of new
problems in semiconductor industry arise. Strict control of quality of wafer during production process is very important
as many factors can influence on it, but the main contribution gives scanner error and mask. Thus at least impact of mask
should be reduced.
In this work we apply rigorous model to predict impact of microstructures to pattern fidelity on wafer. Such
microstructures are commonly generated in quartz layer to control transmittance distribution on photomask. It is shown
that effect from microstructures is not only changing of mask transmittance but also distortion of the pattern fidelity on
wafer. Rigorous modeling gives us possibility to calculate aerial image and CD on wafer in case of presence of microstructures
in the quartz. We vary optical parameters, such as refractive indexes, number, size and location of these
elements in order to reduce the distortion of pattern fidelity on wafer.
Our result allows prediction of the impact of microstructures in photomask on wafer pattern fidelity instead of doing set
of experiments. Moreover, the best conditions for experiment are found and discussed.
As semiconductor features shrink in size and pitch, the pattern placement error at photomask, that is, the registration
becomes more important factor to be reduced. Following ITRS roadmap, the registration for sub-45 nm node is required
to be less than 5 nm but this specification still corresponds to the challengeable goal. Among several reasons to induce
registration, here, we have focused on four major registration errors: e-beam positioning error, patterning effect, pellicle
attachment effect, and sampling error of measurement. We quantify and analyze each error with the help of finite
element modeling and by experiment. Based on these results, we present the current status and the goal of each error for
the roadmap of sub-45 nm node.
KEYWORDS: Mask making, Photomasks, Electron beam lithography, Monte Carlo methods, Control systems, Optical proximity correction, Electron beams, Laser scattering, Scattering, Backscatter
The tight MTT control is required for the mask process of sub-50nm design node due to the complex OPC and
insufficient process margin. The MTT below 5nm is already required for the critical layers. Below 4nm is required for
sub-50nm node. In the viewpoint of this requirement, the MTT control is important for the mask fabrication.
According to the shrinking design node, the linearity is the main issue to satisfy MTT required. In the electron beam (ebeam)
lithography, the linearity results are strongly related to the resolution of the mask process. Isolated and dense
patterns have the different linearity behaviors due to the different contrast mainly caused by the backward scattering
contribution and develop process. Because of this reason, the conventional method of proximity effect correction (PEC)
optimization is unlikely to satisfy the MTT requirement. New PEC optimization is necessary for sub-50nm node.
In this report, new PEC optimization method is proposed. This method reduces the PEC error of conventional
optimization method known as a few nm. Because of the linearity, the error of conventional PEC optimization is
amplified according to the shrinking design. Therefore, the PEC error of conventional method is larger than the MTT
requirement for sub-50nm node. This new method is designed to overcome this problem. It takes into account for the
properties of each layer. Based on the analysis of composition of each layer, the different PEC optimization to fit the
each layer and design node is applied. It is able to be applied for the mask fabrication of sub-50nm memory device. The
improvement of MTT is achieved by the reduction of the PEC error with new PEC optimization.
The optical resolution of Binary mask (BIN) surpasses that of phase shift mask (PSM) when the node size is smaller
than 45nm. Therefore, resolution enhancement technology (RET) of the binary mask has become more important in
order to realize 45nm node lithography. In this paper, we present a unique way to improve the resolution of conventional
binary mask simply by depositing a thin oxide film on the patterned side of the mask. The improvement has been proven
by 3D rigorous simulation and real experiment. The simulation result predicts that the binary mask with a thin oxide
layer would show increased normalized image log slope (NILS) by more than 10 %, compared to the conventional
binary mask. The real experimental evaluation shows even further improved NILS when a thin oxide layer is deposited
on the binary mask. The mask structure with a thin oxide layer turns out to have advantages over the conventional binary
mask in terms of not only improved NILS but also DOF margin aspects. We further investigated resolution enhancement
of the mask structure with a thin oxide layer depending on different duty ratios of the mask pattern.
EUV lithography is one of the most developing and promising lithography techniques. Recently many papers are
focused on defect control of EUV mask multilayer blank, but development of profile metrology is also very important.
2D scatterometry becomes insufficient in conditions of further shrinking of feature size and complication of mask
patterns. To overcome these limitations 3D scatterometry should be used.
In this paper we study the precision of 3D scatterometry measurements of two-dimensional EUV mask features with
variety of geometrical shapes. As in reflectometry of EUV mask we can use only one or a few wavelengths, we have to
take into account intensities of many reflected orders to extract profile precisely. We calculate the library of diffraction
efficiencies for periodic circular, elliptical, and rectangular shaped with rounded corners features using 3D RCWA
method. Then we find the amplitudes of reflected diffraction orders from feature with random arbitrary shape, compare
them with each set of data in the library, and extract the most appropriate shape. After that we analyze whether the
extracted shape is really close to initial arbitrary shape or not.
In some cases extracted shape is not the closest one to the real. It is demonstrated that non-zero value of azimuth angle
of incident light influence on precision of feature shape determination and lead to deterioration of results. Using of
polarized light helps to improve precision of results, but unlike 2D scatterometry the optimal polarization can not be
determined unambiguously. According to received data we provide recommendations for optimal 3D EUV
scatterometry measurements and determine the necessary steps of varying of geometrical parameters for library features.
Hyper numerical aperture (NA) implemented in immersion exposure system makes the semiconductor business enable to enter sub-45nm node optical lithography. Optical proximity correction(OPC) utilizing SRAF has been an essential technique to control critical dimension (CD) and to enhance across pitch performance in sub-wavelength lithography.
Mask lithography, however, is getting more challenging with respect to patterning and processing sub-resolution assist features (SRAFs): the higher aspect ratio of mask structure, the more vulnerable. Mask manufacturing environment for DRAM and Flash becomes harsher mainly due to mask patterning problem especially pattern linearity, which causes pattern broken, inspection issue, and finally CD issue on wafer. When a pattern in relatively isolated pitches has small or large assist features, the assist features may bring unexpected CD or print on wafer. A frequency-preserving assist bar solution is the most preferred one, but it is difficult to realize for opaque assist features due to printability.
In this paper, we propose a new type assist feature dubbed "Phase-shifted Assist Bar" to improve process window and to solve the resolution constraint of mask at sub-45nm manufacturing process node. The concept of phase-shift assist bar is applying phase-shift to SRAF realized with trench structure on general mask, such as Binary and Attenuated Phase-Shifted Mask (Att.PSM). The characteristics of phase-shift assist bar are evaluated with rigorous 3D lithography simulation and analyzed through verification mask, which is containing hugely various size and placement of main and assist feature. The analysis of verification mask has been done with aerial image verification tool. This work focuses on the performance of phase-shift assist bar as a promising OPC technique for "immersion era" in terms of resolution enhancement technique, optical proximity correction, and patterning on mask.
As the pattern half pitch on the mask gets shorter than the wavelength by smaller device design rule, 3-D effect of the mask pattern topology becomes greater. The resolution approaches to that of the attenuated Phase Shift Mask (attPSM), when pattern size is smaller than 45 nm node. The binary mask was therefore selected due to the simple fabrication process and the advantage with no-haze, and its performance was evaluated both numerically and experimentally by newly designing the mask structure that may have mask immersion effects. This new mask can be made by depositing transparent oxide materials on a conventional patterned binary mask. When the change of NILS (Normalized Image Log Slope) was checked quantitatively according to duty ratio and oxide thickness, the NILS increased more than 10% on the average from the simulation and about 10-30% from the experiment, when compared with the binary mask. In other words, the mask structure with the transparent oxide layer improves the NILS and has the advantage in the DOF margin. Since only the deposition process is required after the binary mask is made, the manufacturing is relatively simple.
The purpose of this paper is to do the direct comparison of between the novel chrome-less phase shift mask (CLM), which is suggest by Chen et. al. recently, and attenuated phase shift mask which has been in the main stream of DRAM lithography. Our study is focused on the question of whether the CLM technology has a potential advantages compared with attenuated PSM, so as to substitute the position of it in 0.3 k1 lithography era of DRAM. Firstly, some basic characteristics of both masks are studied, that is intensity distribution of diffraction orders and optical proximity effect etc. And then mask layouts are optimized through the resist patterning simulation for various critical layers of DRAM with CLM and attenuated PSM, respectively. Resolution performances such as exposure latitude and DOF margin and mask error enhancing factor etc. are compared through the simulations and experiments. In addition, it is also studied in the point of mask manufacturing of CLM such as phase control issues, defect printability, mask polarity, and so forth.
As the pattern size becomes smaller, double or multi exposure is required unless the epochal solutions for overcoming the limits of present lithography system do appear or are discovered. ArF DET (double exposure technology) strategy based on manual OPC with in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method to extend the limitation of current lithography. HOST requires no additional procedures and separate layout optimizations of each region in terms of OPC are enough. Furthermore, it is possible to change illumination condition of each region and the overlap between two regions with ease. The results from the simulation are pattern size and profile of each condition according to the defous and misregistration. 0.63 NA ArF Scanner and Clariant resist is used for wafer process. The resist was coated on Clariant organic BARC using 0.24 um thickness. Dipole illumination for cell region and annular illumination for peripheral region are used. Cell region contains 0.20 um pitch duty pattern and peripheral region 0.24 um pitch duty pattern. The boundary of two regions is investigated in view of validity of stitching itself. The layout of reticles used as the cell and peripheral region are optimized by OPC, respectively and then, additional OPC was treated to the boundary, i.e., stitching area to compensate the cross term of the boundary caused by separate and independent optimization with OPC in the cell and the peripheral regime. The final patterns were acquired by defining the cell at first and the peripheral region secondly with different defocus and registration in respect to the cell. The actual data on wafer are presented according to defocus and one region's overlay offset relatively to the other region. And the outstanding matching between simulation results and in-line data are shown. Lithography process window for stable patterning is thoroughly investigated in view of depth of focus, energy latitude, registration between two stitched regions and stitching itself in the boundary. It is found from the experiment that total DOF of DE (double exposure) is 0.5 um and the total EL of DE is 10.0% in this paper. At present, it is very difficult to ensure stable process margin for the sub-0.10 um patterning. But there is a promising technology called stitching with special optimization. In addition, this technology will be nominated as an eternal candidate process whenever our lithography is in the adversity at the limits of his days.
We have evaluated 0.33k1 ArF lithography using 0.63NA scanner to develop 100 nm DRAM. ArF resist problems were resist pattern shrinkage during CD SEM measurement, resist pattern collapse during wet development and poor etch resistance. Off-Site Measurement (OSM) method has been developed for decreasing pattern shrinkage. With OSM method, 8nm of CD shrinkage was down to 2nm for 100nm L/S patterns. We have found a proper BARC material that prevents resist patterns falling down. Lack of etch resistance was compensated by hard mask. With W/SiN hard mask, acrylate- type resist patterns were transferred well into W/poly-Si gate patterns. We have simulated process window of critical DRAM cell patterns (isolation, gate, bit line contact, storage node) in the simple off-axis illumination (OAI) and optical proximity correction (OPC) conditions based on single exposure. Simulation results were verified by lithography tests and it turned out that 0.33k1 process was possible with exposure latitude of above 10% and focus latitude of more than 0.4 micrometers . 0.33k1 ArF lithography was successfully implemented into 100 nm DRAM with CD uniformity of 10nm (3 (sigma) ) and overlay accuracy of 30 nm (mean +3 (sigma) ). We have also evaluated double exposure technique using dipole illumination targeting 90 nm in order to see the possibility of 0.29k1 process. 0.29k1 process was also likely to be possible, although some specific improvements were recommended for the wider process window. From the simulation and resist patterning results, we believe that 0.85 NA lens will be able to extend ArF lithography into 75 nm by single exposure technology using crosspole illumination (0.33k1 process) and 65 nm by double exposure technology using dipole and crosspole illumination (0.29k1 process).
With smaller features sizes and higher pattern densities on high-end mask for DUV lithography, pattern fidelity on mask features becomes essential for optical proximity correction (OPC) performance. But some degree of corner rounding on the mask is inevitable even using the latest writing tool. The corner rounding radius on mask is mainly determined by the resolution of writing tool, mask resist process and chrome etching process following. In this paper, we will first discuss corner rounding impact for two-dimensional pattern applied OPC. Secondly modeling mask patterning process by applying diffused aerial image model (DAIM). Thirdly we will compare mask simulation results and mask SEM image for various mask masking process. Finally, we will examine a new simulation method to enhance the accuracy of wafer patterning simulation by using not CAD layout but mask layout extracted from mask patterning simulation.
As ArF process will be substituted for KrF process at below 0.13 um node, it is time to study CD budget of mask error in ArF lithography. The purpose of this study is to investigate printability of ArF mask defects and corresponding effective specification in repeating cell. Mask defects in regularly repeated pattern were classified as point defect, line defect, and are defect, for convenience's sake, according to their sizes and lithographic explanations. Based on such classification, test reticle (ArF attenuated PSM) was manufactured in our captive mask shop. After exposed at a nominal dose and e-beam cured, each defects was inspected to extract effective specification for ArF process. MNPD (maximum non-printable defect) sizes of various duty patterns were manifested in point defect. In line defect and area defect, as the base pattern CD and duty ratio changed, the slope (MEF) of linear fitting was obtained. Maximum CD deviation from mean CD could be calculated from it. Mask CD budget was considered as 50% of total wafer CD error (10% of target) for mask spec generation. Experimental result was compared with DAIM (diffused aerial image model)-based simulation result because experiment had the error that arose from e-beam curing.
Recently, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as cell region to the resolution limit of exposure tools. Therefore it is necessary to apply optical proximity correction (OPC) not only to the patterns in cell region but also to those in peripheral region. It is impossible to apply manual OPC method in peripheral region. Because the peripheral region is composed of random patterns with large data volume, and it takes too long execution time with manual OPC. For random pattern OPC in peripheral region, automatic OPC tool is required. Now for the automatic OPC tool, model-based and rule-based methods are developed for the commercial use. In this paper, the effectively applicable process is discussed using model-based method in automatic OPC at the sub-0.10 micrometer design rule in ArF lithography. For the application of automatic OPC tool at the design rule of sub-0.10 micrometer and ArF process in memory devices the following problem should be cleared. In small size of design rule, we should consider not only pattern fidelity but also process margin such as depth of focus (DOF) and exposure latitude (EL) at the cell OPC. But automatic OPC tool is insufficient to be applied for cell region OPC, because it considers not process margin but pattern fidelity and it has low accuracy using much approximation model to reduce layout correction time. To solve this problem, we suggest a full chip OPC process using both automatic OPC tool and the manual OPC method using the novel lithography simulation model (Diffused Aerial Image Model, DAIM). DAIM is available to predict wafer pattern and process margin of cell, its accuracy is verified in ArF process as in KrF process. We could see small standard deviation error between experiment and DAIM in ArF process using various line or space patterns, which is about 9 nm at binary intensity mask (BIM). So the manual OPC with DAIM resulted in the wide process margin and good pattern fidelity overcoming the limitation of automatic OPC tool. However it is necessary to correlate energy level of DAIM for cell region OPC with that of the model in the automatic OPC tool for peripheral region OPC, because cell and peripheral region are exposed with the same exposure dose in stepper or scanner. In case of ArF process, we could see the small difference of energy level and standard deviation error, which is about 1.4%, 2 nm at BIM and 6.3%, 3 nm at half-tone phase shift mask (PSM), between DAIM and automatic OPC tool. As the result of using DAIM and automatic OPC tool simultaneously at full chip OPC, we could see improved results from cell to peripheral region at the sub-0.10 micrometer design rule in ArF lithography.
The patterning potentialities of sub-100nm pattern for ArF lithography was evaluated with conventional alternating PSM (alt-PSM) for dense lines and spaces (L/S) and phase edge PSM (PE-PSM) for isolated lines of memory device. In dense L/S pattern,110nm pattern was defined with relatively small depth of focus(DOF) window(~ 0.2 ?m) due to phase error of mask. As pattern sizes was changed from 130nm to 200nm, critical dimension (CD) difference between two neighboring spaces was varied and it was assumed that micro loading effect was occurred in Qz etching. The linearity was guaranteed to dense L/S of 110nm and isolated line of 90nm, and Iso-Dense bias was controlled within 15nm. The 60nm and 70nm isolated lines of PE-PSM ware defined with good process windows in the case of OA_X size(X-direction size of Cr open area) of 0.5 ?m. The 55nm isolated line was also defined. The pattern shift of isolated lines was occurred with 4~7nm as phase of mask was varies within 190 ~ 200 ° . Though the alt-PSM with high numerical aperture (NA) for ArF lithography was strong candidates for sub-1 OOnm lithography of memory device, the issues of mask fabrication such as tighter phase control and minimizing etch loading effect would be big obstacles. On the contrary, there were many possibilities of sub-100nm patterning in PE-PSM with good process windows, however tighter control of pattern shift due to phase error must be studied intensively.
Optical lithography at resolution limit is a non-linear pattern transfer. One of the important issue is a mask critical dimension control because of nonlinear amplification of mask critical dimension error during image transferring on wafer. This amplification of mask error is called the MEF. This mask error factor has been widely used as an important parameter for indicating tighter CD control for the photomask for low-kl lithography generation.
Recently, the miniaturization of the design rule of memory devices pushes the minimum feature sizes down to sub- wavelengths of the exposure tools. The design of a memory device comprises not only the dense patterns with critical small size in the cell region but also the random patterns in the peripheral region; the latter also need sub- wavelength lithography technology as well as the former. And the optical proximity correction (OPC) has been strongly required for the random patterns in the peripheral region where the same energy is exposed as in the cell region. Therefore, the high accuracy of simulation model used in the OPC is necessary for the full chip OPC tools. However traditional aerial image simulation has a limitation to the application due to its lack of accuracy because it does not take into account a resist process. We introduced novel lithography simulation model in 1998, which describes resist process by diffusion and chemically amplification function.
Ultimate limitation of lithography has been studied by using the diffused aerial image model (DAIM). Assuming that only the 0th and 1st order diffraction beams in the off-axis illumination technique contribute to the resist patterns, aerial image is calculated for dense line and space patterns. And then DAIM is applied to achieve final image. By using this diffused aerial image, exposure latitude and mask error effect can be analyzed quantitatively. In the case of perfect image, which can be achieved from, for example, diffraction free x-ray lithography or electron beam lithography without Coulomb repulsion and back scattering effect, same approaches are possible to get the exposure latitude and mask error effect. Under the validation of DAIM, most important parameter, which characterizes dense L/S patterns, is the diffusion length of acid. In order to realize sub-o.1 micrometers pattern with enough process margins, it is required to enlarge exposure latitude and to reduce mask error effect. Therefore, reducing h acid diffusion length of chemical amplification resist (CAR) or new conceptual resist instead of CAR will be needed for sub-0.1 micrometers era.
The defect control of the attenuated-PSM is compared with that of the conventional binary intensity mask (BIM), because the fabrication process for the att-PSM tends to generate more defects than that of the BIM. To repair a defective att. PSM, a similar method used for BIM has been applied. However, this process may cause degradation of pattern fidelity with the repair pattern on the mask are transferred on the wafer, if the transmission and phase of repaired area are not well controlled. In this paper, we have investigated the effect of repairing process on the pattern fidelity to define contact holes using a KrF lithography with an att. PSM. The defects in the various distances form contact hole patterns and of various sizes were repaired. The experimental printability and simulation data from an aerial image model were compared for repaired defects. And the repair tool reliability and the simulation accuracy of the att. PSM was examined using CD-SEM. From the experimental results, repaired defects having larger size than the threshold. One or within a certain range from the pattern induced the pattern deformation. Therefore, the size of defect and the distance between the pattern and defect should be considered in repair process for the Att. PSM fabrication. Based on the experimental and simulation results, the requirements for the repair tool will be proposed.
Optical proximity correction technique has been studied. The occurrence of proximity effect in the optical lithography is composed of an element caused by diffraction of light, which can be explained by aerial image simulation, and an element caused by resist process, in which acid diffusion is a major factor causing non-linearity. In the case of very thin resist, absorbed energy that generates the acid can be described by two-dimensional instead of three-dimensional distribution. Under this simple assumption, acid diffusion by post exposure bake is equivalent to the diffusion of aerial image, and chemical amplification can be analytically described also. Modified aerial image including diffusion and chemical amplification, we call it diffused aerial image, can give the information for patterning status directly. Therefore, diffused aerial image model can explain experimental results very well compared to the expectation by using aerial image only without loss of simplicity and calculation speed.
An alternating phase shift mask is very effective to memory devices which have highly repeated patterns. In order to apply the alternating phase shift mask to real device, we have investigated the design problems such as proximity effect, phase contradiction, phase transition, and linewidth variation. We also design various hard defects in order to check defect printability on wafer. Using i-line lithography with an alternating phase shift mask, we obtain useful focus latitude of 1.2micrometers for bit line of 256M DRAM. Deep UV alternating phase shift mask is used for isolation patterns with design rule of 0.16micrometers . The experimental and simulation results for phase-induced problems and defect printability on wafer are described in detail.
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