In 5nm node, even minor process variation in extreme ultraviolet lithography (EUVL) can bring significant impact to the device performance. Except for the overlay and critical dimension uniformity (CDU), EUV specific effects, such as shadowing, three-dimensional mask effect (M3D), and stochastic effects, must also be understood in processing, modeling, and optical proximity correction (OPC). We simulate those variabilities using a calibrated model and compare it to what is observed on the wafer. The interconnect path of Metal1-Via1-Metal2 is studied by using a silicon-calibrated resistivity model to analyze the related overlap area and the electrical resistance. The approach allows us to quantify the impact of EUVL process by investigating the individual contribution of each patterning process variations.
We have been utilizing rigorous simulation software in order to predict the alignment mark signal quality and mark contrast variation induced by processes changes reliably. We have run simulations in order to understand which parameters influence alignment mark quality most and to determine the important parameters that can be manipulated in order to improve it. Simulation of alignment signals (also referred to as waveforms) has been done for resist marks and etched marks, coated and uncoated, as well as in presence of increasing topography complexity. To validate simulation analysis, mark signal collection for different processes (and/or variations of those) and products has been carried out; cross sections have also been generated.
Line width roughness (LWR) remains a critical issue when moving towards smaller feature sizes in EUV lithography. At the same time, negative-tone develop (NTD) resist has become a promising process to get wide process margin at narrow trenches and for block mask layers in optical lithography. Here, we present a study on printing behavior of an EUV NTD resist which was exposed at IMEC on the AMSL NXE:3100 EUV tool. In particular, we analyzed the line width roughness, which was found to be pattern dependent. We calibrated a stochastic resist model to the experimental CD and LWR data. The resulting model was used to analyze and understand the pattern dependent LWR behavior. Simulation results for different LWR process window between iso trench, dense line and iso line was verified with measurement results.
The extension of 193nm immersion lithography to the 14nm node and beyond directly encounters a
significant reduction in image quality. One of the consequences is that the resist profile varies noticeably,
impacting the already limited process window. Resist top-loss, top-rounding, T-top and footing all play
significant roles in the subsequent etch process. Therefore, a reliable rigorous model with the capability to
correctly predict resist 3D (R3D) profiles is acquiring higher importance. In this paper, we will present a
calibrated rigorous model of a negative-tone develop resist. Resist profiles can be well simulated through
focus and dose, and cases that match well to the experimental wafer data are validated. Such a model can
not only provide early investigation of insights into process limitation and optimization, but can also
complement existing OPC models to become R3D-aware in process development.
We analyzed the lithographic performance of a double patterning technology (DPT) with resist freeze
(LFLE) process for printing dense contact holes (CH). For the first time, we quantified the contribution
of the substrate - frozen resist and topography effects. The impact on image contrast, and NILS was
studied through-pitch.
In comparing to the case of a uniform L/S, the image through-pitch performance is degraded in LFLE
CH. This is resulted from diffraction by the underlying topography and materials. The process steps
(between first-and-second Litho) cause additional challenges in the fabrication of CHs using DPT.
Current inspection of the process effects only observes the reflected signal for position alignment. We
have introduced simulations of a phase change in polarized signal (ellipsometry) after first and second
lithography steps for suggesting a new methodology for detection and validation of topography changes
in DPT flow. In DPT the first Litho result is fabricated in substrate, so the analysis of ellipsometry signal
can be applied to sensitively detect correlations between two steps.
The spectroscopic ellipsometry simulation results were shown; α and β parameters demonstrate the
sensitivity w.r.t. substrate topography, by changing the incident optical direction from x-z to y-z plane.
This represents the correlation between parameters observed by respective Litho steps of perpendicular
orientation.
Furthermore, ellipsometry signal was used to optimize the "frozen" resist n and k values w.r.t aerial
image performance, which can be fed back to DPT design.
Concluding, the information obtained by ellipsometry is useful to characterize substrate topography in
DPT design.
Double patterning (DP) was investigated for logic layout by using a rigorous three-dimensional (3D) wafer-topography/lithography simulator with water immersion lithography. With increasing complexity of the DP process, the 3D wafer-topography effect of stack structure must be considered, because of its impact to lithography. The main purpose of this paper is to present how to optimize both process and design to ensure overlap and connectivity of split patterns by solving electro-magnetic field distribution in wafer substrate, as well as resist region. A process window was analyzed varying not only focus, dose, and split masking layers, but also considering topography of substrate stack structures, which cause local reflectivity variations. Arbitrary 45 nm logic layout including an L-shaped pattern was analyzed. The process window of the second litho step was analyzed. Due to the reflection from the hard mask (HM, result of the first litho step), the process window was restricted and became smaller. The other option suggests that swapping the first and second litho masks is a better choice, with respect to the impact of wafer topography. The optimization of the stack process condition was analyzed by using the contour plot of reflectivity, as functions of n, k, and thickness of materials inside the bottom anti-reflective coating. The concept of extended normalized image log slope considering local reflectivity variation from wafer process is able to explain the variation of resist sidewall slope and exposure latitude.Therefore, it is useful to analyze connectivity at the stitching point by using a 3D wafer-topography/lithography simulator and to optimize the combination of the DP process and layout stitching design. Furthermore, as a design of an advanced process, litho-develop litho-etch was simulated.
Currently, EUV and double patterning (DP) are competing technologies for the 22nm hp node. The goal of this paper is
to perform a case study and explore resolution limits on a 32nm contact hole array. In order to investigate the resolution
limit for a DP process quantitatively, considering the substrate topography structure is crucial. We applied wafertopography/
lithography simulation to study the relevant effects in detail. To perform a comparative study between ArF
DP and EUV lithography we first analyzed the resolution limit for DP process. We investigated the performance of a
LDLD and a LFLE (litho-freeze-litho-etch) process by decreasing pitch until the resolution limit was reached. The
possible minimum x- pitch (with y-parallel line, first mask) is 85nm, the minimum y-pitch generated for the second litho
step with x-parallel lines is 90nm. This x-y anisotropic phenomenon is caused by the second litho step, where oblique
incident light propagating through space regions contributes to total image. The bulk image distribution is sensitive to
the material in the spacer region, therefore further process optimization is possible by tuning material properties.
Alternatively the fabrication of 32nm size contact holes with EUV lithography was simulated. Pattern shift due to
shadowing, aberrations and flare effects have been considered. A pitch of 64nm (1:1) can be realized at low flare levels,
but corrections for shadowing and flare are essential. Based on this quantification the gap of possible minimum pitch
between DP and EUV are discussed. Furthermore relation between DP topography effect and SMO are discussed.
Double patterning (DP) was investigated for logic layout by using rigorous 3D wafer-topography/
lithography simulator with water immersion lithography. With increasing complexity of DP process,
3D wafer-topography effect of stack structure must be considered, because of its impact to
lithography.
The main purpose of this paper is to present how to optimize both process and design to ensure
overlap and connectivity of split pattern, by solving electro-magnetic field distribution in wafer
substrate as well as resist region.
Process window was analyzed varying not only focus, dose and split masking layers, but also
considering topography of substrate stack structures, which cause local reflectivity variations.
Arbitrary 45nm logic layout including L-shape pattern was analyzed. Process window of second
Litho step was analyzed. Due to reflection from Hard Mask, HM (the first Litho step) the process
window was restricted and became smaller. The other option, swapping first and second Litho
masks is a better choice with respect to impact of wafer topography.
The optimization of stack process condition was analyzed by using contour plot of reflectivity, as
functions of n, k and thickness of materials inside BARC. The concept of Extended NILS
considering local reflectivity variation from wafer process is able to explain the variation of resist
sidewall slope and Exposure Latitude. Therefore, it is useful to analyze connectivity at stitching
point by using 3D wafer-topography/ lithography simulator and to optimize the combination of DP
process and layout stitching design. Furthermore as design of advanced process, LLE
(Litho-Litho-Etch), with resist freezing was simulated.
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