CMOS image sensor (CIS) is used in various applications such as surveillance cameras, automobile cameras, mobile phones and digital single lens reflex (DSLR). The photodetectors used in the CIS are p-n junction photodiodes, pinned photodiodes, MOSFET-type photodetectors, and bipolar junction transistor-type photodetectors. A CMOS active pixel sensor (APS) with adjustable sensitivity is presented which uses MOSFET-type photodetector with a built-in transfer gate. The sensitivity of the APS using the MOSFET-type photodetector is much higher than that of the APS using the pn junction photodiode, since the MOSFET-type photodetector is composed of a floating-gate tied to an n-well and the photocurrent is amplified by the MOSFET. Although the APS using conventional MOSFET-type photodetector cannot control the current flowing through the channel, the APS using MOSFET-type photodetector with a built-in transfer gate can control the photocurrent by adjusting the pulse level of the transfer gate. Since the transfer gate controls the amount of electric charge that is transferred from the drain of the MOSFET to the integration node, the sensitivity of the APS can be adjusted by controlling the pulse level of the transfer gate. Using the high sensitivity characteristic of MOSFETtype photodetector and the function of transfer gate, the APS maintains high sensitivity under low intensity of illumination and adjusts to low sensitivity under high intensity of illumination. These results might be useful for extending the dynamic range of the APS using the MOSFET-type photodetector. The CMOS APS was designed and fabricated using 2-poly 4-metal 0.35 μm standard process and its performance was evaluated.
Effects of light intensity on disparity for depth extraction in monochrome CMOS image sensor with offset pixel apertures are investigated. The technology consumes less power, since it does not use external light sources. The offset pixel apertures are integrated in each pixel of the monochrome CMOS image sensor to acquire the disparity for depth extraction. Because the monochrome CMOS image sensor does not contain color filters, the height of the pixel is lower than that of the CMOS image sensor with color filters, resulting in a better disparity. The monochrome CMOS image sensor with offset pixel apertures was designed and fabricated using 0.11 μm CMOS image sensor process. Disparity of the sensor has been measured under various light intensities. The sensor might be useful for three-dimensional imaging in outdoor applications with a simple structure.
A CMOS image sensor with off-center circular apertures for two-dimensional (2D) and three-dimensional (3D) imaging was fabricated, and its performance was evaluated, including the results of 2D and 3D images. The pixel size, based on a four-transistor active pixel sensor with a pinned photodiode, is 2.8 μm × 2.8 μm. Disparate images as well as focused images for depth calculation can be obtained using the designed pixel pattern. The pixel pattern is composed of one white subpixel with a left-offset circular aperture, a blue pixel, a red pixel, and another white subpixel with a right-offset circular aperture. The proposed technique was verified by simulation and measurement results using a point light source. In addition, the depth image was implemented by calculating the depth information from the 2D images.
Effects of aperture size on the performance of CMOS image sensor with pixel aperture for depth extraction are investigated. In general, the aperture size is related to the depth resolution and the sensitivity of the CMOS image sensor. As the aperture size decreases, the depth resolution is improved and the sensitivity decreases. To optimize the aperture size, optical simulation using the finite-difference time-domain method was implemented. The optical simulation was performed with various aperture sizes from 0.3 μm to 1.1 μm and the optical power with the incidence angle as a function of the aperture size was evaluated. Based on the optical simulation results, the CMOS image sensor was designed and fabricated using 0.11 μm CMOS image sensor process. The effects of aperture size are investigated by comparison of the simulation and the measurement results.
The 3-dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. Many techniques have been reported for 3D imaging using various methods such as time of fight (TOF), stereo vision, and structured light. These methods have limitations such as use of light source, multi-camera, or complex camera system. In this paper, we propose the offset pixel aperture (OPA) technique which is implemented on a single chip so that the depth can be obtained without increasing hardware cost and adding extra light sources. 3 types of pixels including red (R), blue (B), and white (W) pixels were used for OPA technique. The aperture is located on the W pixel, which does not have a color filter. Depth performance can be increased with a higher sensitivity because we use white (W) pixels for OPA with red (R) and blue (B) pixels for imaging. The RB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Previously, we proposed the pixel aperture (PA) technique based on the depth from defocus (DFD). The OPA technique is expected to enable a higher depth resolution and range compared to the PA technique. The pixels with a right OPA and a left OPA are used to generate stereo image with a single chip. The pixel structure was designed and simulated. Optical performances of various offset pixel aperture structures were evaluated using optical simulation with finite-difference time-domain (FDTD) method.
In this paper, we propose a pixel averaging current calibration algorithm for reducing fixed pattern noise due to the deviation of bolometer resistance. To reduce fixed pattern noise (FPN), averaging current calibration algorithm by which output current of each bolometer reference pixel is averaged by the averaging current calibration is suggested. The principle of algorithm is that average dark current of reference pixel array is subtracted by a dark current of each active pixel array. After that, the current difference with information of pixel deviation is converted to voltage signal through signal processing. To control the current difference of pixel deviation, a proper calibration current is required. Through this calibration algorithm, nano-ampere order dark currents with small deviations can be obtained. Sensor signal processing is based on a pipeline technique which results in parallel processing leading to very high operation. The proposed calibration algorithm has been implemented by a chip which is consisted of a bolometer active pixel array, a bolometer reference pixel array, average current generators, line memories, buffer memories, current-to-voltage converters (IVCs), a digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). Proposed bolometerresistor pixel array and readout circuit has been simulated and fabricated by 0.35μm standard CMOS process.
Recently, CMOS image sensors (CISs) have become more and more complex because they require high-performances such as wide dynamic range, low-noise, high-speed operation, high-resolution and so on. First of all, wide dynamic range (WDR) is the first requirement for high-performance CIS. Several techniques have been proposed to improve the dynamic range. Although logarithmic pixel can achieve wide dynamic range, it leads to a poor signal-to-noise ratio due to small output swings. Furthermore, the fixed pattern noise of logarithmic pixel is significantly greater compared with other CISs. In this paper, we propose an optimized linear-logarithmic pixel. Compared to a conventional 3-transistor active pixel sensor structure, the proposed linear-logarithmic pixel is using a photogate and a cascode MOSFET in addition. The photogate which is surrounding a photodiode carries out change of sensitivity in the linear response and thus increases the dynamic range. The logarithmic response is caused by a cascode MOSFET. Although the dynamic range of the pixel has been improved, output curves of each pixel were not uniform. In general, as the number of devices increases in the pixel, pixel response variation is more pronounced. Hence, we optimized the linear-logarithmic pixel structure to minimize the pixel response variation. We applied a hard reset method and an optimized cascode MOSFET to the proposed pixel for reducing pixel response variation. Unlike the conventional reset operation, a hard reset using a p-type MOSFET fixes the voltage of each pixel to the same voltage. This reduces non-uniformity of the response in the linear response. The optimized cascode MOSFET achieves less variation in the logarithmic response. We have verified that the optimized pixel shows more uniform response than the conventional pixel, by both simulation and experiment.
A 3dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. In this paper, extraction of depth information for 3D imaging using pixel aperture technique is presented. An active pixel sensor (APS) with in-pixel aperture has been developed for this purpose. In the conventional camera systems using a complementary metal-oxide-semiconductor (CMOS) image sensor, an aperture is located behind the camera lens. However, in our proposed camera system, the aperture implemented by metal layer of CMOS process is located on the White (W) pixel which means a pixel without any color filter on top of the pixel. 4 types of pixels including Red (R), Green (G), Blue (B), and White (W) pixels were used for pixel aperture technique. The RGB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RGB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Size of the pixel for 4-tr APS is 2.8 μm × 2.8 μm and the pixel structure was designed and simulated based on 0.11 μm CMOS image sensor (CIS) process. Optical performances of the pixel aperture technique were evaluated using optical simulation with finite-difference time-domain (FDTD) method and electrical performances were evaluated using TCAD.
In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.
A novel high-sensitivity active pixel sensor (APS) with a variable threshold photodetector has been presented and for the first time, a simple SPICE model for the variable threshold photodetector is presented. Its SPICE model is in good agreement with measurements and is more simpler than the conventional model. The proposed APS has a gate/body-tied PMOSFET-type photodetector with an overlapping control gate that makes it possible to control the sensitivity of the proposed APS. It is a hybrid device composed of a metal-oxide-semiconductor field-effect transistor (MOSFET), a lateral bipolar junction transistor (BJT) and a vertical BJT. Using sufficient overlapping control gate bias to operate the MOSFET in inversion mode, the variable threshold photodetector allows for increasing the photocurrent gain by 105 at low light intensities when the control gate bias is -3 V. Thus, the proposed APS with a variable threshold photodetector has better low-light-level sensitivity than the conventional APS operating mode, and it has a variable sensitivity which is determined by the control gate bias. The proposed sensor has been fabricated by using 0.35 μm 2-poly 4-metal standard complementary MOS (CMOS) process and its characteristics have been evaluated.
In recent times, much research in the field of complementary metal oxide semiconductor (CMOS) image sensors (CISs) regarding plasmonic color filters (PCFs) has been reported. In this paper, we investigated the influence of vertically asymmetrical metallic apertures on the extraordinary optical transmission of PCFs. We designed a structural model of the asymmetric cylindrical aperture. In addition, we simulated the spectral variation in the wavelength transmission. For the simulation, we used a commercial computer simulation tool utilizing the FDTD method. SiO2 was used as the substrate insulator, top-side insulator, and the fill material in the cylindrical aperture. We applied Au as the metal layer; dispersion information for Au was derived from the Lorentz–Drude model. We also presented the electric field distribution under several different conditions at the peak wavelength of the calculated transmission spectrum. Furthermore, we determined the transmittance spectral characteristics and the peak transmittance under several different conditions.
In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied
(GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured
using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+-
polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT
photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be
increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that
is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A
CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip-
flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low
power consumption and high speed operation with the ability to switch back and forth between a binary mode and an
analog mode.
In this paper, we proposed the plasmonic color filters to decrease ambient light errors on active type dual band infrared image sensors for a large-area multi-touch display system. Although the strong point of the touch display system in the area of education and exhibition there are some limits of the ambient light. When an unexpected ambient light incidents into the display the touch recognition system can make errors classifying the touch point in the unexpected ambient light area. We proposed a new touch recognition image sensor system to decrease the ambient light error and investigated the optical transmission properties of plasmonic color filters for IR image sensor. To find a proper structure of the plasmonic color filters we used a commercial computer simulation tool utilizing finite-difference time-domain (FDTD) method as several thicknesses and whit the cover passivation layer or not. Gold (Au) applied for the metal film and the dispersion information associated with was derived from the Lorentz-Drude model. We also described the mechanism applied the double band filter on the IR image sensors.
This paper presents a novel high-sensitivity and wide dynamic range complementary metal oxide semiconductor
(CMOS) active pixel sensor (APS) with an overlapping control gate. The proposed APS has a high-sensitivity gate/bodytied
(GBT) photodetector with an overlapping control gate that makes it possible to control the sensitivity of the
proposed APS. The floating gate of the GBT photodetector is connected to the n-well and the overlapping control gate is
placed on top of the floating gate for varying the sensitivity of the proposed APS. Dynamic range of the proposed APS is
significantly increased due to the output voltage feedback structure. Maximum sensitivity of the proposed APS is 50
V/lux•s in the low illumination range and dynamic range is greater than 110 dB. The proposed sensor has been fabricated
by using 2-poly 4-metal 0.35 μm standard CMOS process and its characteristics have been evaluated.
We investigated optical properties of subwavelength patterned metal gratings for photonic device application. It was known that optical transmittance of metal films with subwavelength periodic hole arrays can be controlled by applying a dielectric overlay to the film and the films can act as wavelength or frequency selective filters. Following advancement in lithography technology it could be applied up to complementary metal oxide semiconductor (CMOS) image sensors (CIS) by patterning metal layers placed on each pixel’s photo detective device. However it is not easy to replace organic color filters applied on CIS up to date because the standard CIS structure has multi-metal layers, thick dielectric layers, and too thick metal layers. In this work, we explore possibility to integrate the metal film into a CIS chip and present an alternative proposal by computer simulation utilizing finite-difference time-domain (FDTD) method. We applied aluminum (Al) for the metal film and the dispersion information associated with Al was derived from the Lorentz-Drude model. We expect that this work could contribute to search to apply subwavelength patterned metal gratings to photonic devices.
In this study, the influence of an active cell design on the power conversion efficiency (PCE) of a monolithic organic
photovoltaic (OPV) module was investigated using experimental methods and circuit simulation. For circuit simulation
using computer simulation-based study, the organic PV cell was described by a circuit-based two-diode model and the
modules were simulated under several conditions including shading effect, diode model parameters, series resistance and
shunt resistance, etc. A unit organic PV cell as a reference device and four types of monolithic organic PV modules with
different active cell length were fabricated together on the same glass substrate. The characteristics of the fabricated unit
OPV cell were measured and the electrical parameters were extracted to use them for the simulation of four types of
monolithic organic PV modules. To analyze the influence of OPV cell design on the PCE of monolithic organic PV
modules, the current-voltage (I-V) characteristic curves and the PCEs of the four type monolithic OPV modules with
different active cell length were obtained and compared with the simulated results. The simulated I-V curves were
matched well with the measured I-V curves for the four types of monolithic organic PV modules with different active
cell length. The highest PCE of the monolithic OPV module was 2.86 % with the active cell length of 11.6 mm. We
expect that this work is meaningful to enhance the performance of a monolithic OPV module to a certain extent and it
offers a method to design a high-efficiency large-area monolithic OPV module.
Various approaches have been utilized to extend the dynamic range of the CMOS image sensor, which are based on a
linear-logarithmic CIS, overflow integration capacitor and multiple sampling or individual pixel resetting. These
approaches, however, suffer from noise, nonlinearity, lower sensitivity, reduced operating speed and lower resolution. In
order to overcome these problems, we have previously proposed a dynamic range extension method by combining output
signals from two photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity
photodiode. The proposed active pixel sensor has been fabricated by using 2-poly 4-metal standard CMOS process and
its characteristics have been measured. It is found that charges in the high- and low-sensitivity photodiodes could be
mixed each other and the lost image information of the high-sensitivity photodiode could be regenerated using the
charges in the low-sensitivity photodiode, as shown by simulation results. Dynamic range extension of the proposed
active pixel sensor has been experimentally verified.
A dynamic range (DR) extension technique based on a 3-transistor (3-Tr.) active pixel sensor (APS) and dual image
sampling has been proposed. The feature of the proposed APS was that the APS used two photodiodes with different
sensitivities, a high-sensitivity photodiode and a low-sensitivity photodiode. Operation of the proposed APS was
simulated by using a 128×128 pixel array. Compared with previously proposed wide DR (WDR) APS, the proposed
approach has several advantages; no-external equipments or signal processing for combining images, no-additional timerequirement
for additional charge accumulation, adjustable DR extension and no temporal disparity.
This paper presents a commercial metal-oxide-semiconductor field-effect transistor (MOSFET)-based biosensor with a
gold extended-gate electrode for the electronic detection of C-reactive protein (CRP). From a component point of view,
the commercial MOSFET-based biosensor consists of a commercial MOSFET with a socket for connecting the gold
electrode which was fixed on a printed circuit board (PCB) and a reaction-vessel module which was assembled with the
gold electrode and the Ag/AgCl reference electrode. The gold electrode with only one gold layer was fabricated on a
glass substrate simply and it was used as the extended-gate metal to form a self-assembled monolayer (SAM). The
binding of the CRP to anti-CRP was detected by measuring the electrical characteristics of the biosensor. Variation of
the drain current before and after the interaction of CRP and anti-CRP was about 1.2mA on the measured IDS-VDS and
real-time characteristics. The concentration of the CRP solution was adjusted to 10μg/ml by dissolving in PBS. The
change of surface voltage of the gold extended-gate electrode was about 30mV by IDS-VGS characteristic curve of the
commercial MOSFET. Therefore, it is confirmed that the detection of CRP is possible by measuring the drain current of
the commercial MOSFET. The proposed biosensor might open up a new possibility for FET-based biosensors with lowcost
and simple construction. It is expected that the commercial MOSFET-based biosensor with the gold extended-gate
electrode could also be used for detecting various biomarkers by modifying the surface of the gold extended-gate
electrode.
In this paper, we present a wide dynamic range active pixel sensor (APS) using an external charge pump circuit. The
proposed pixel exhibits improved dynamic range through the compensated threshold voltage of a reset MOSFET. We
confirmed that the light level which is the saturated output voltage in the proposed APS is about 170,000 lux, which is
36% higher than that of a conventional APS. The proposed APS is fabricated by using 2-poly 4-metal 0.35 &mgr; standard
CMOS process. The unit pixel consists of an n+ diffusion / p-substrate photodiode, three NMOSFETs and the charge
pump circuit which consists of two NMOSFETs and two capacitors.
CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help
develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of
the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a
resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed
with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a
standard CMOS technology. The experimental results have been nicely matched with our prediction.
In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The
key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge
accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision
chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the
vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is
commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive
network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a
160×120 pixel array was fabricated using a 0.35 &mgr;m double-poly four-metal CMOS technology, and its operation was
experimentally investigated.
In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate
that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 &mgr;m 2-poly 4-
metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 &mgr;m pixels. The unit pixel has a
configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer
gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer
gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 103 A/W
without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination
as low as 5 lux.
In this article, we report a MOSFET-type biosensor assembled in a polydimethylsiloxane (PDMS) micro-fluidic channel for the electrical detection of nano-scale biomolecules. The MOSFET-type sensor was fabricated on the basis of standard complementary metal oxide semiconductor (CMOS) technology. Au which has a chemical affinity with thiol by forming a self-assembled monolayer (SAM) was used as the gate metal. In order to apply to the hybrid micro-flow-system for a prototype lab-on-a-chip, the PDMS layer with the micro-channel was aligned along with the sensing area of the MOSFET device. Thiol which was injected into the micro-fluidic channel was detected by measuring the electrical characteristics of the MOSFET sensor in both ex-situ and in-situ due to the negative charge of thiol.
In this paper, we propose a MOSFET-type biosensor in which an extended gate is formed on the bottom of silicon microfluidic channel across the (111) silicon sidewall. Electrical characteristics of the sensor were measured in the solution containing streptavidin-biotin protein complexes. The connection between MOSFET and micro-fluidic channel system could be achieved with the proposed device, offering merits of isolation between the device and solution, compatibility with the integrated circuit technology and applicability in the micro total analysis system. The device was fabricated on the basis of the semiconductor integrated circuit fabrication and micro-electro mechanical system technology. Au was used as the extended gate metal to form a self-assembled monolayer of thiol which was used to immobilize streptavidin and biotin. Atomic force microscopy was used to observe the presence of biomolecules on Au electrode.
The noise problem, such as the fixed pattern noise (FPN) due to the process variation, should be considered when designing a vision chip. In this paper, we proposed an edge detection circuit based on biological retina using an offset-free column readout circuit (OFCRC) to reduce the FPN occurring in the photo-detector. The OFCRC consists of one source follower, one capacitor and five transmission gates. Thus, it is simpler than a conventional correlated double sampling (CDS) circuit. A vision chip for edge detection has been designed and fabricated using a 0.35μm 2-poly 4-metal CMOS process and its output characteristics have been investigated.
Numerical increment of analog circuits causes power consumption to increase and requires a larger chip area. In designing an analog complementary-metal-oxide-semiconductor (CMOS) vision chip for edge detection, power consumption should be considered. It restricts the number of the edge detection circuit which is based on the edge detection mechanism of vertebrate retina. In this paper, we applied electronic switches to an analog CMOS vision chip for edge detection to reduce the power consumption. Also, we propose a method to implement vision chip with higher resolution, which is to separate pixels for edge detection into a 128×128 photodetector array and a 1×128 edge detection driving circuit array. The capability to minimize power consumption was investigated by SPICE. Estimated power consumption with 128×128 pixels was below 20mW.
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