The performance shortcomings of multipurpose compute engines have stirred recent excitement in specialized processors, preempted by GPUs. Simultaneously, computational complexity theory NP 'hard' problems scaling as O(n^k) require new hardware solutions. This presents an opportunity for photonic information processors (PIP) building on photonic integration through recent foundry developments. The value proposition for PIPs exist via optical parallelism, small capacitive charging of OE devices, 10's of ps short propagation delays, a natural convolution via optical interference, and an O(n)-scaling Fourier transform. Based on a recently developed photonic NxN router, here we present two photonic processors; a) the residual arithmetic nanophotonic computer (RANC), and b) a reconfigurable graph processor, the latter being a computing-in-switching (CIS) paradigm. PIPs operate with time-of-flight, once the processor is configured (e.g. setting phase), which is on the order of 10-100 ps given the mm-scale photonic integration footprints. This high bandwidth, however challenges the electronic-optic I/O bottleneck. To address this, we further discuss an optical front-end DAC with <100 ps delay enabled by a 2x2 electro-optic switch.
Residue number system (RNS) enables dimensionality reduction of an arithmetic problem by representing a large number as a set of smaller integers, where the number is decomposed by prime number factorization. These reduced problem sets can then be processed in- dependently and in parallel, thus improving computational efficiency and speed. Here we show an optical RNS hardware representation based on integrated nanophotonics. The digit-wise shifting in RNS arithmetic is expressed as spatial routing of an optical signal in 2×2 hybrid photonic-plasmonic switches. Here the residue is represented by spatially shifting the input waveguides relative to the routers’ outputs, where the moduli are represented by the number of waveguides. By cascading the photonic 2×2 switches, we design a photonic RNS adder and a multiplier forming an all-to- all sparse directional network. The advantage of this photonic arithmetic processor is the short (10’s ps) computational execution time given by the optical propagation delay through the integrated nanophotonic router. Furthermore, we show how photonic processing in- the-network leverages the natural parallelism of optics such as wavelength-division-multiplexing in this RNS processor. A key application for such a photonic RNS engine is the functional analysis of convolutional neural networks.
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