Dr. John A. Allgair Profile

Dr. John A. Allgair

CTO & Interim President

SPIE Involvement:

Conference Program Committee | Author | Editor

Publications (52)

Proceedings Article | 22 February 2021 Presentation

High volume manufacturing metrology needs at and beyond the 5 nm node

Benjamin Bunday, Ndubuisi Orji, John Allgair

Proceedings Volume 11611, 116110F (2021) https://doi.org/10.1117/12.2584555

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Proceedings Article | 10 April 2013 Paper

Implementation of hybrid metrology at HVM fab for 20nm and beyond

Alok Vaid, Lokesh Subramany, Givantha Iddawela, Carl Ford, John Allgair, Gaurav Agrawal, John Taylor, Carsten Hartig, Byung Cheol (Charles) Kang, Cornel Bozdog, Matthew Sendelbach, Paul Isbester, Limor Issascharoff

Proceedings Volume 8681, 868103 (2013) https://doi.org/10.1117/12.2012339

KEYWORDS: Metrology, Semiconducting wafers, Critical dimension metrology, Transmission electron microscopy, Etching, Process control, Reactive ion etching, Data modeling, High volume manufacturing

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SPIE Journal Paper | 5 June 2012

Time-dependent electron-beam-induced photoresist shrinkage effects

Benjamin Bunday, Aaron Cordes, Carsten Hartig, John Allgair, Alok Vaid, Eric Solecky, Narender Rana

JM3, Vol. 11, Issue 02, 023007, (June 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.2.023007

KEYWORDS: Photoresist materials, Metrology, Critical dimension metrology, Time metrology, Semiconducting wafers, Scanning electron microscopy, Lithography, Etching, Diffractive optical elements, Optical proximity correction

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Proceedings Article | 4 April 2012 Paper

Hybrid metrology solution for 1X-node technology

Alok Vaid, Alexander Elia, Mark Kelling, John Allgair, Carsten Hartig, Peter Ebersbach, Erin McLellan, Matthew Sendelbach, Nedal Saleh, Narender Rana, Hiroki Kawada, Toru Ikegami, Masahiko Ikeno, Takahiro Kawasaki, Cornel Bozdog, Helen Kim, Elad Arnon, Roy Koret, Igor Turovets

Proceedings Volume 8324, 832404 (2012) https://doi.org/10.1117/12.916940

KEYWORDS: Line edge roughness, Scatterometry, Data modeling, Metrology, Critical dimension metrology, Metals, Semiconducting wafers, Extreme ultraviolet, Scatter measurement

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SPIE Journal Paper | 1 October 2011

Holistic metrology approach: hybrid metrology utilizing scatterometry, critical dimension-atomic force microscope and critical dimension-scanning electron microscope

Alok Vaid, Bin Bin Yan, Yun Tao Jiang, Mark Kelling, Carsten Hartig, John Allgair, Peter Ebersbach, Matthew Sendelbach, Narender Rana, Ahmad Katnani, Erin McLellan, Charles Archie, Cornel Bozdog, Helen Kim, Michael Sendler, Susan Ng, Boris Sherman, Boaz Brill, Igor Turovets, Ronen Urensky

JM3, Vol. 10, Issue 04, 043016, (October 2011) https://doi.org/10.1117/12.10.1117/1.3655726

KEYWORDS: Metrology, Scatterometry, Critical dimension metrology, Semiconducting wafers, Data modeling, Atomic force microscopy, Transmission electron microscopy, Inspection, 3D metrology

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Proceedings Article | 20 April 2011 Paper

Tool-to-tool matching issues due to photoresist shrinkage effects

Benjamin Bunday, Aaron Cordes, Carsten Hartig, John Allgair, Alok Vaid, Eric Solecky, Narender Rana

Proceedings Volume 7971, 79710B (2011) https://doi.org/10.1117/12.881400

KEYWORDS: Photoresist materials, Metrology, Semiconducting wafers, Lithography, Critical dimension metrology, Time metrology, Etching, Optical proximity correction, Manufacturing, Polymers

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Proceedings Article | 29 March 2011 Paper

A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM

Alok Vaid, Bin Bin Yan, Yun Tao Jiang, Mark Kelling, Carsten Hartig, John Allgair, Peter Ebersbach, Matthew Sendelbach, Narender Rana, Ahmad Katnani, Erin Mclellan, Chas Archie, Cornel Bozdog, Helen Kim, Michael Sendler, Susan Ng, Boris Sherman, Boaz Brill, Igor Turovets, Ronen Urensky

Proceedings Volume 7971, 797103 (2011) https://doi.org/10.1117/12.881632

KEYWORDS: Metrology, Critical dimension metrology, Scatterometry, Semiconducting wafers, Metals, Transmission electron microscopy, Data modeling, Atomic force microscopy, Inspection

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SPIE Journal Paper | 1 January 2011

Measurement traceability and quality assurance in a nanomanufacturing environment

Ndubuisi Orji, Ronald Dixson, Aaron Cordes, Benjamin Bunday, John Allgair

JM3, Vol. 10, Issue 1, 013006, (January 2011) https://doi.org/10.1117/12.10.1117/1.3549736

KEYWORDS: Metrology, Calibration, Environmental sensing, Quality measurement, Manufacturing, Control systems, Data processing, Standards development, Measurement devices, Error analysis

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Proceedings Article | 24 August 2010 Paper

Multipurpose instrument calibration standard for particle beam, scanned probe and optical microscopy: NIST reference material (RM) 8820

Michael Postek, András Vladar, William Keery, Michael Bishop, Benjamin Bunday, John Allgair

Proceedings Volume 7767, 77670D (2010) https://doi.org/10.1117/12.861595

KEYWORDS: Calibration, Scanning electron microscopy, Silicon, Contamination, Standards development, Scatterometry, Metrology, Lithography, Electron microscopes, Microscopes

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Proceedings Article | 3 June 2010 Paper

NEW scanning electron microscope magnification calibration reference material (RM) 8820

Michael Postek, András Vladár, William Keery, Michael Bishop, Benjamin Bunday, John Allgair

Proceedings Volume 7729, 77290D (2010) https://doi.org/10.1117/12.859118

KEYWORDS: Calibration, Scanning electron microscopy, Electron microscopes, Silicon, Contamination, Standards development, Lithography, Electroluminescent displays, Metrology, Scatterometry

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Proceedings Article | 2 April 2010 Paper

Reference material (RM) 8820: a versatile new NIST standard for nanometrology

Michael Postek, Andras Vladar, William Keery, Michael Bishop, Benjamin Bunday, John Allgair

Proceedings Volume 7638, 76381B (2010) https://doi.org/10.1117/12.848037

KEYWORDS: Calibration, Scanning electron microscopy, Silicon, Contamination, Standards development, Metrology, Lithography, Electron microscopes, Electroluminescent displays, Scatterometry

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Proceedings Article | 2 April 2010 Paper

Electron-beam induced photoresist shrinkage influence on 2D profiles

Benjamin Bunday, Aaron Cordes, John Allgair, Daniel Bellido Aguilar, Vasiliki Tileli, Bradley Thiel, Yohanan Avitan, Ram Peltinov, Mayaan Bar-Zvi, Ofer Adan, Konstantin Chirko

Proceedings Volume 7638, 76381L (2010) https://doi.org/10.1117/12.846991

KEYWORDS: Photoresist materials, Data modeling, Scattering, Monte Carlo methods, Lithography, Critical dimension metrology, Metrology, Laser scattering, Scanning electron microscopy, Extreme ultraviolet lithography

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For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. Also, such smaller feature sizes will require thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMI's CD-SEM Unified Specification. A model for resist shrinkage, while derived elsewhere, was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) before e-beam exposure. With these parameters and exhaustive measurements, a fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized features. This work was extended in yet another paper in which we presented a 1-D model for resist shrinkage that can be used to curve-fit to shrinkage curves. Calibration of parameters to describe the photoresist material and the electron beam were all that were required to fit the model to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. In this paper, we extend this work yet again to a 2-D model of a trapezoidal photoresist profile. This model thus allows CD shrinkage in thin photoresist to be solved, which is now of great interest for upcoming realistic lithographic processing. It also allows us to predict the change in resist profile with electron dose and the influence of initial resist profile on shrinkage characteristics. In this work, the results from the previous paper will be shown to be consistent with numerically simulated results, thus lending credibility to these papers' postulations. Also, results from this 2-D profile model can also give clues as to how we might, in the future, model the shrinkage of contour edges of 3-D shapes. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of future photoresist measurement, as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

Proceedings Article | 21 August 2009 Paper

Measurement traceability and quality assurance in a nanomanufacturing environment

N. George Orji, Ronald Dixson, Aaron Cordes, Benjamin Bunday, John Allgair

Proceedings Volume 7405, 740505 (2009) https://doi.org/10.1117/12.826606

KEYWORDS: Metrology, Calibration, Environmental sensing, Quality measurement, Manufacturing, Control systems, Data processing, Measurement devices, Time metrology, Error analysis

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Proceedings Article | 24 March 2009 Paper

Monitoring measurement tools: new methods for driving continuous improvements in fleet measurement uncertainty

Eric Solecky, Chas Archie, Matthew Sendelbach, Ron Fiege, Mary Zaitz, Dmitriy Shneyder, Carlos Strocchia-rivera, Andres Munoz, Srinivasan Rangarajan, William Muth, Andrew Brendler, Bill Banke, Bernd Schulz, Carsten Hartig, Jon-Tobias Hoeft, Alok Vaid, Mark Kelling, Benjamin Bunday, John Allgair

Proceedings Volume 7272, 72721H (2009) https://doi.org/10.1117/12.814089

KEYWORDS: Semiconducting wafers, Metrology, Scatterometry, Process control, Calibration, Manufacturing, Overlay metrology, Time metrology, Atomic force microscopy

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Ever shrinking measurement uncertainty requirements are difficult to achieve for a typical metrology toolset, especially over the entire expected life of the fleet. Many times, acceptable performance can be demonstrated during brief evaluation periods on a tool or two in the fleet. Over time and across the rest of the fleet, the most demanding processes often have measurement uncertainty concerns that prevent optimal process control, thereby limiting premium part yield, especially on the most aggressive technology nodes. Current metrology statistical process control (SPC) monitoring techniques focus on maintaining the performance of the fleet where toolset control chart limits are derived from a stable time period. These tools are prevented from measuring product when a statistical deviation is detected. Lastly, these charts are primarily concerned with daily fluctuations and do not consider the overall measurement uncertainty. It is possible that the control charts implemented for a given toolset suggest a healthy fleet while many of these demanding processes continue to suffer measurement uncertainty issues. This is especially true when extendibility is expected in a given generation of toolset. With this said, there is a need to continually improve the measurement uncertainty of the fleet until it can no longer meet the needed requirements at which point new technology needs to be entertained. This paper explores new methods in analyzing existing SPC monitor data to assess the measurement performance of the fleet and look for opportunities to drive improvements. Long term monitor data from a fleet of overlay and scatterometry tools will be analyzed. The paper also discusses using other methods besides SPC monitors to ensure the fleet stays matched; a set of SPC monitors provides a good baseline of fleet stability but it cannot represent all measurement scenarios happening in product recipes. The analyses presented deal with measurement uncertainty on non-measurement altering metrology toolsets such as scatterometry, overlay, atomic force microscopy (AFM) or thin film tools. The challenges associated with monitoring toolsets that damage the sample such as the CD-SEMs will also be discussed. This paper also explores improving the monitoring strategy through better sampling and monitor selection. The industry also needs to converge regarding the metrics used to describe the matching component of measurement uncertainty so that a unified approach is reached regarding how to best drive the much needed improvements. In conclusion, there will be a discussion on automating these new methods3,4 so they can complement the existing methods to provide a better method and system for controlling and driving matching improvements in the fleet.

Proceedings Article | 24 March 2009 Paper

Phenomenology of electron-beam-induced photoresist shrinkage trends

Benjamin Bunday, Aaron Cordes, John Allgair, Vasiliki Tileli, Yohanan Avitan, Ram Peltinov, Maayan Bar-zvi, Ofer Adan, Eric Cottrell, Sean Hand

Proceedings Volume 7272, 72721B (2009) https://doi.org/10.1117/12.816249

KEYWORDS: Photoresist materials, Data modeling, Monte Carlo methods, Lithography, Metrology, Scanning electron microscopy, Critical dimension metrology, Semiconducting wafers, Roentgenium, Contamination

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For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 45 nm node and beyond, new lithography techniques are being considered, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print 45 nm node (and beyond) feature widths and pitches. In a previous paper [1], we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMI's CD-SEM Unified Specification [2]. A model for resist shrinkage, while derived elsewhere [3], was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) from before e-beam exposure. The ability to know this original CD is the most desirable result; in this work, the ability to use extrapolation to solve for a given original CD value was also experimentally validated by CD-atomic force microscope (AFM) reference metrology. Historically, many different conflicting shrinkage results have been obtained among the many works generated through the litho-metrology community. This work, backed up by an exhaustive dataset, will present an explanation that makes sense of these apparent discrepancies. Past models for resist shrinkage inherently assumed that the photoresist line is wider than the region of the photoresist to be shrunk [3], or, in other words, the e-beam never penetrates enough to reach all material in the interior of a feature; consequently, not all photoresist is affected by the shrinkage process. In actuality, there are two shrinkage regimes, which are dependent on resist feature CD or thickness. Past shrinkage models are true for larger features. However, our results show that when linewidth becomes less than the eventual penetration depth of the e-beam after full shrinkage, the apparent shrinkage magnitude decreases while shrinkage speed accelerates. Thus, for small features, most shrinkage occurs within the first measurement. This is crucial when considering the small features to be fabricated by immersion lithography. In this work, the results from the previous paper [1] will be shown to be consistent with numerically simulated results, thus lending credibility to the postulations in [1]. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of both dry and immersion ArF lithographies as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

Proceedings Article | 9 September 2008 Paper

Accuracy considerations for critical dimension semiconductor metrology

N. Orji, R. Dixson, B. Bunday, J. Allgair

Proceedings Volume 7042, 70420A (2008) https://doi.org/10.1117/12.796372

KEYWORDS: Metrology, Calibration, Transmission electron microscopy, Semiconductors, Standards development, Lithography, Atomic force microscope, Line edge roughness, Atomic force microscopy, Carbon nanotubes

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Proceedings Article | 24 March 2008 Paper

Characterization of CD-SEM metrology for iArF photoresist materials

Benjamin Bunday, Aaron Cordes, N. Orji, Emil Piscani, Dan Cochran, Jeff Byers, John Allgair, Bryan Rice, Yohanan Avitan, Ram Peltinov, Maayan Bar-zvi, Ofer Adan

Proceedings Volume 6922, 69221A (2008) https://doi.org/10.1117/12.774317

KEYWORDS: Photoresist materials, Lithography, Metrology, Scanning electron microscopy, Semiconducting wafers, Atomic force microscopy, Roentgenium, Critical dimension metrology, Extreme ultraviolet, Cadmium

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Proceedings Article | 22 March 2008 Paper

Toward accurate feature shape metrology

Ndubuisi Orji, Ronald Dixson, Benjamin Bunday, John Allgair

Proceedings Volume 6922, 692208 (2008) https://doi.org/10.1117/12.774426

KEYWORDS: Calibration, Transmission electron microscopy, Metrology, Atomic force microscope, Process control, Atomic force microscopy, Head, Electron microscopes, Binary data, Feature extraction

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Proceedings Article | 5 April 2007 Paper

Major trends in extending CD-SEM utility

Benjamin Bunday, John Allgair, Kyoungmo Yang, Shunsuke Koshihara, Hidetoshi Morokuma, Alex Danilevsky, Cindy Parker, Lorena Page

Proceedings Volume 6518, 651835 (2007) https://doi.org/10.1117/12.714193

KEYWORDS: Pattern recognition, Critical dimension metrology, Metrology, Optical proximity correction, Semiconducting wafers, Reticles, Inspection, Scanning electron microscopy, Yield improvement, Detection and tracking algorithms

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Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, along with even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions continue to shrink, local line width variation influences the statistical confidence of a measured CD's representation of the process. A feature, called "Average CD (ACD)," measures multiple targets within the field of view (FOV). ACD allows not only measurements of a single data point representing one discrete feature, but also sampling of the mean and variance of the process. These two applications, automatic recipe creation and ACD, are combined in the second version of the DesignGauge software, which is available for the latest-generation Hitachi S-9380II CD-SEMs. DesignGauge V2 is not only capable of offline recipe creation and CD-SEM control, but it also has the ability to directly transfer design-based recipes into standard CD-SEM recipes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which yields much needed improvement to production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, reducing engineering time required to generate recipes, and improving CD-SEM utilization. Another benefit of the application is an improvement in recipe robustness over conventional direct image-based pattern recognition. This work will show an extensive evaluation of DesignGauge V2, including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation, and recipe execution. The impact of ACD will also be evaluated.

Proceedings Article | 5 April 2007 Paper

TEM calibration methods for critical dimension standards

Ndubuisi Orji, Ronald Dixson, Domingo Garcia-Gutierrez, Benjamin Bunday, Michael Bishop, Michael Cresswell, Richard Allen, John Allgair

Proceedings Volume 6518, 651810 (2007) https://doi.org/10.1117/12.713368

KEYWORDS: Transmission electron microscopy, Calibration, Standards development, Crystals, Electron microscopes, Scanning electron microscopy, Metrology, Silicon, Atomic force microscope, Image resolution

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One of the key challenges in critical dimension (CD) metrology is finding suitable calibration standards. Over the last few years there has been some interest in using features measured with the transmission electron microscope (TEM) as primary standards for linewidth measurements. This is because some modes of TEM can produce lattice-resolved images having scale traceability to the SI (Systeme International d'Unites or International System of Units) definition of length through an atomic lattice constant. As interest in using calibration samples that are closer to the length scales being measured increases, so will the use of these TEM techniques. An area where lattice-traceable images produced by TEM has been used as a primary standard is in critical dimension atomic force microscope (CD-AFM) tip width calibration. Two modes of TEM that produce crystal lattice-traceable images are high resolution transmission electron microscope (HR-TEM) and high angle annular dark field scanning transmission electron microscope (HAADF-STEM). HR-TEM produces lattice-traceable images by interference patterns of the diffracted and transmitted beams rather than the actual atomic columns, while HAADF-STEM produces direct images of the crystal lattice. The difference in how both of these techniques work could cause subtle variations in the way feature edges are defined. In this paper, we present results from width samples measured using HR-TEM and HAADF-STEM. Next we compare the results with measurements taken from the same location by two different CD-AFMs. Both of the CD-AFM instruments used for this work have been calibrated using a single crystal critical dimension reference material (SCCDRM). These standards, developed by the National Institute of Standards and Technology (NIST) and SEMATECH, used HR-TEM for traceable tip-width calibration. Consequently, the present work and the previous SCCDRM work provide a mutual cross-check on the traceability of the width calibration. Excellent agreement was observed.

Proceedings Article | 5 April 2007 Paper

SEM metrology for advanced lithographies

Benjamin Bunday, John Allgair, Bryan Rice, Jeff Byers, Yohanan Avitan, Ram Peltinov, Maayan Bar-zvi, Ofer Adan, John Swyers, Roni Shneck

Proceedings Volume 6518, 65182B (2007) https://doi.org/10.1117/12.714203

KEYWORDS: Lithography, Photoresist materials, Metrology, Deep ultraviolet, Extreme ultraviolet lithography, Extreme ultraviolet, Scanning electron microscopy, 193nm lithography, Semiconducting wafers, Scanners

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Proceedings Article | 5 April 2007 Paper

Fundamental limits of optical critical dimension metrology: a simulation study

Richard Silver, Thomas Germer, Ravikiran Attota, Bryan Barnes, Benjamin Bunday, John Allgair, Egon Marx, Jay Jun

Proceedings Volume 6518, 65180U (2007) https://doi.org/10.1117/12.716604

KEYWORDS: Scatterometry, Reflectivity, Polarization, Finite-difference time-domain method, Data modeling, Diffraction, Oxides, Silicon, Critical dimension metrology, Amorphous silicon

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Proceedings Article | 5 April 2007 Paper

The coming of age of tilt CD-SEM

B. Bunday, J. Allgair, E. Solecky, C. Archie, N. Orji, J. Beach, O. Adan, R. Peltinov, M. Bar-zvi, J. Swyers

Proceedings Volume 6518, 65181S (2007) https://doi.org/10.1117/12.714214

KEYWORDS: Photoresist materials, Semiconducting wafers, Metrology, Critical dimension metrology, Scanning electron microscopy, Scanners, Lithography, Process control, Calibration

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The need for 3D metrology is becoming more urgent to address critical gaps in metrology for both lithographic and etch processes. Current generation lithographic processing (ArF source, where λ=193 nm) sometimes results in photoresist lines with re-entrant profiles or T-topping, as do many etch processes. A re-entrant profile misleads top-down metrology into reading the critical dimension (CD) as too large. Recent advances in gate process technology also raise challenges to traditional top-down metrology. One such example is the FinFET, which is truly a 3D device with 3D metrology needs. The ability to measure the bottom width of a profile is crucial for process control. Recently, tilt-beam critical dimension-scanning electron microscopy (CD-SEM) applications have been developed to measure the bottom CD of such features, using the tilted-view to "see" the bottom, avoiding the feature's larger top. This is an important achievement, as the bottom of a profile is the main feature of interest in many processes. Estimation of sidewall angle (SWA) is also important. For several years, tilt-beam CD-SEM has been an available technique for this measurement, with limited adoption by the litho-metrology community. However, in this paper we will explore another method to use the tilt feature to measure average sidewall angle, based on edgewidth measurement and the assumption of basic trapezoidal profile and known height and combined with the ability to sample multiple-features. While it will not provide exact profile shape, this technique can be quite useful in providing average profile information and will definitely exhibit good throughput. Samples used will be photoresist and etched FinFET structures to measure sidewall angles. Correlations of the results to a traceable CD-atomic force microscopy (AFM) reference measurement system are provided. Conclusions will show preliminary findings of the readiness of tilt-beam CD-SEM for measuring profile and, by extension, the status of measuring 3D structures such as FinFETs, and using CD-SEM as a direct control of lithographic tooling for T-topped photoresist profiles.

Proceedings Article | 5 April 2007 Paper

Realizing "value-added" metrology

Benjamin Bunday, Pete Lipscomb, John Allgair, Dilip Patel, Mark Caldwell, Eric Solecky, Chas Archie, Jennifer Morningstar, Bryan Rice, Bhanwar Singh, Jason Cain, Iraj Emami, Bill Banke, Alfredo Herrera, Vladamir Ukraintsev, Jerry Schlessinger, Jeff Ritchison

Proceedings Volume 6518, 65181K (2007) https://doi.org/10.1117/12.714216

KEYWORDS: Metrology, Overlay metrology, Inspection, Semiconducting wafers, Process control, Yield improvement, Critical dimension metrology, Optical proximity correction, Etching, Lithography

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The conventional premise that metrology is a "non-value-added necessary evil" is a misleading and dangerous assertion, which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled "value-added" processing steps in lithography and etch, such that they can be considered integral parts of the processes. Various key trends in modern, state-of-the-art processing such as optical proximity correction (OPC), design for manufacturability (DFM), and advanced process control (APC) are based, at their hearts, on the assumption of fine-tuned metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities to create value through the engineering of tight and targetable process distributions. Such distributions make possible predictability in speed-sorts and in other parameters, which results in high-end product. Additionally, significant reliance has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology team using quality practices. This paper will explore the relationships among present and future trends and challenges in metrology, including equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology will be demonstrated to have shifted to "key enabler of large revenues," debunking the out-of-date premise that metrology is "non-value-added." Examples used will be from critical dimension (CD) metrology, overlay, films, and defect metrology.

SPIE Journal Paper | 1 April 2007

Progress on implementation of a reference measurement system based on a critical-dimension atomic force microscope

Ndubuisi Orji, Ronald Dixson, Angela Martinez, Benjamin Bunday, John Allgair, Theodore Vorburger

JM3, Vol. 6, Issue 02, 023002, (April 2007) https://doi.org/10.1117/12.10.1117/1.2728742

KEYWORDS: Calibration, Standards development, Error analysis, Scanners, Atomic force microscope, Silicon, Semiconductor manufacturing, Semiconductors, Metrology, Semiconducting wafers

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Proceedings Article | 27 March 2007 Paper

Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations

Kevin Lucas, Chris Cork, Jonathan Cobb, Brian Ward, Martin Drapeau, Charlie Zhang, John Allgair, Mike Kling, Mike Rieger

Proceedings Volume 6520, 65200N (2007) https://doi.org/10.1117/12.715166

KEYWORDS: Optical lithography, Optical proximity correction, Error analysis, Resolution enhancement technologies, SRAF, Lithography, OLE for process control, Photomasks, Manufacturing, Metrology

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An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed. In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

Proceedings Article | 24 March 2006 Paper

Yield enhancement methodologies for 90-nm technology and beyond

John Allgair, Todd Carey, James Dougan, Tony Etnyre, Nate Langdon, Brooke Murray

Proceedings Volume 6152, 615208 (2006) https://doi.org/10.1117/12.656616

KEYWORDS: Semiconducting wafers, Inspection, Process control, Semiconductors, Yield improvement, Metals, Manufacturing, Polishing, Etching, Semiconductor manufacturing

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Proceedings Article | 24 March 2006 Paper

Small feature accuracy challenge for CD-SEM metrology: physical model solution

Benjamin Bunday, John Allgair, Ofer Adan, Aviram Tam, Sergey Latinski, Guy Eytan

Proceedings Volume 6152, 61520S (2006) https://doi.org/10.1117/12.659779

KEYWORDS: Scanning electron microscopy, Metrology, Cadmium, 3D modeling, Stereoscopy, Critical dimension metrology, Transmission electron microscopy, Silicon, Algorithm development, Calibration

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Proceedings Article | 24 March 2006 Paper

Calibrating optical overlay measurements

W. Lipscomb, J. Allgair, B. Bunday, M. Bishop, R. Silver, R. Attota, M. Stocker

Proceedings Volume 6152, 615211 (2006) https://doi.org/10.1117/12.659597

KEYWORDS: Overlay metrology, Scanning electron microscopy, Atomic force microscopy, Calibration, Metrology, Interfaces, Semiconducting wafers, Line edge roughness, Optical testing, Wafer-level optics

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Proceedings Article | 24 March 2006 Paper

Litho-metrology challenges for the 45-nm technology node and beyond

John Allgair, Benjamin Bunday, Mike Bishop, Pete Lipscomb, Ndubuisi Orji

Proceedings Volume 6152, 61520C (2006) https://doi.org/10.1117/12.659059

KEYWORDS: Overlay metrology, Metrology, Critical dimension metrology, Scanning electron microscopy, Semiconducting wafers, Amorphous silicon, Reticles, Calibration, Manufacturing, Lithography

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Proceedings Article | 24 March 2006 Paper

Automated CD-SEM recipe creation: a new paradigm in CD-SEM utilization

Benjamin Bunday, William Lipscomb, John Allgair, Kyoungmo Yang, Shunsuke Koshihara, Hidetoshi Morokuma, Lorena Page, Alex Danilevsky

Proceedings Volume 6152, 61521B (2006) https://doi.org/10.1117/12.659759

KEYWORDS: Pattern recognition, Semiconducting wafers, Optical proximity correction, Scanning electron microscopy, Computer aided design, Lithography, Metrology, Scatterometry, Reticles, Precision measurement

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Proceedings Article | 24 March 2006 Paper

Progress on implementation of a CD-AFM-based reference measurement system

Ndubuisi Orji, Angela Martinez, Ronald Dixson, John Allgair

Proceedings Volume 6152, 61520O (2006) https://doi.org/10.1117/12.653287

KEYWORDS: Calibration, Error analysis, Standards development, Scanners, Liquid crystal lasers, Semiconductors, Dimensional metrology, Atomic force microscope, Metrology, Silicon

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Proceedings Article | 19 August 2005 Paper

Improvement in total measurement uncertainty for gate CD control

Benjamin Bunday, Osman Sorkhabi, Youxian Wen, Ajit Paranjpe, Paul Terbeek, John Allgair, Amy Peterson

Proceedings Volume 5878, 58780M (2005) https://doi.org/10.1117/12.616344

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Amorphous silicon, Finite element methods, Metrology, Scatterometry, Data modeling, Oxides, Calibration, Reticles

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Proceedings Article | 10 May 2005 Paper

CD SEM metrology macro CD technology: beyond the average

Benjamin Bunday, Di Michelson, John Allgair, Aviram Tam, David Chase-Colin, Asaf Dajczman, Ofer Adan, Michael Har-Zvi

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.600133

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Process control, Metrology, Etching, Cadmium, Lithography, Line width roughness, Statistical analysis

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Proceedings Article | 10 May 2005 Paper

Specifications, methodologies, and results of evaluation of optical critical dimension scatterometer tools at the 90nm CMOS technology node and beyond

Benjamin Bunday, Amy Peterson, John Allgair

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.600115

KEYWORDS: Semiconducting wafers, Finite element methods, Critical dimension metrology, Metrology, Signal to noise ratio, Calibration, Reticles, Lithography, Line width roughness, Interference (communication)

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Proceedings Article | 24 May 2004 Paper

Determination of optimal parameters for CD-SEM measurement of line-edge roughness

Benjamin Bunday, Michael Bishop, Donald McCormack, John Villarrubia, Andras Vladar, Ronald Dixson, Theodore Vorburger, N. Orji, John Allgair

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535926

KEYWORDS: Line edge roughness, Line scan image sensors, Line width roughness, Edge roughness, Image segmentation, Critical dimension metrology, Metrology, Edge detection, Image quality, Tolerancing

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The measurement of line-edge roughness (LER) has recently become a topic of concern in the litho-metrology community and the semiconductor industry as a whole. The Advanced Metrology Advisory Group (AMAG), a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST), has a project to investigate LER metrics and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed, standardized solution for implementation. The 2003 International Technology Roadmap for Semiconductors (ITRS) has included a new definition for roughness. The ITRS envisions root mean square measurements of edge and width roughness. There are other possible metrics, some of which are surveyed here. The ITRS envisions the root mean square measurements restricted to roughness wavelengths falling within a specified process-relevant range and with measurement repeatability better than a specified tolerance. This study addresses the measurement choices required to meet those specifications. An expression for the length of line that must be measured and the spacing of measurement positions along that length is derived. Noise in the image is shown to produce roughness measurement errors that have both random and nonrandom (i.e., bias) components. Measurements are reported on both UV resist and polycrystalline silicon in special test patterns with roughness typical for those materials. These measurements indicate that the sensitivity of a roughness measurement to noise depends importantly both on the choice of edge detection algorithm and the quality of the focus. Measurements are less sensitive to noise when a model-based or sigmoidal fit algorithm is used and when the images are in good focus. Using the measured roughness characteristics for UV resist lines and applying the ITRS requirements for the 90 nm technology node, the derived expression for sampling length and sampling interval implies that a length at least 8 times the node (i.e., 720 nm) must be measured at intervals of 7.5 nm or less.

Proceedings Article | 24 May 2004 Paper

Results of benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node

Benjamin Bunday, Michael Bishop, John Allgair

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535960

KEYWORDS: Semiconducting wafers, Line edge roughness, Scanning electron microscopy, Pattern recognition, Contamination, Finite element methods, Standards development, Metrology, Lithography, Critical dimension metrology

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The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH Manufacturing Initiative (ISMI) consortium’s Member Companies and from the National Institute of Standards (NIST). The AMAG wrote and, in 2002, with CD-SEM supplier involvement, updated the “Unified Advanced CD-SEM Specification for Sub-130nm Technology (Version 2002)” to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2003 International Technology Roadmap for Semiconductors, and also conveys member companies’ other collective needs to vendors. Through applying this specification during the mid-2003 timeframe, a benchmarking effort of the currently available advanced CD-SEMs has been performed. These results are presented here. The AMAG Unified Specification includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter included in the benchmark, and, when applicable, prescribes a target specification compatible with the ITRS and methodologies compatible with the demands of 90nm technology. Parameters to be considered include: •Precision, Repeatability and Reproducibility •Accuracy, Apparent Beam Width and Resolution •Charging and Contamination •Tool-to-Tool Matching •Pattern Recognition and Navigation Accuracy •Throughput •Instrumentation Outputs •Tool Automation and Utility •Precision and Accuracy of Profile Measurement •Precision and Accuracy of Roughness Measurement. Previous studies under this same project have been published, with the initial version of the International Sematech Unified Specification in 1998, and multi-supplier benchmarks in 1999 and 2001. The results for the 2003 benchmark will be shown and compared to the ITRS, and composite viewpoints showing these 2003 benchmark results compared to the past results are also shown, demonstrating interesting CD-SEM industry trends.

Proceedings Article | 10 July 2003 Paper

Applications of image diagnostics to metrology quality assurance and process control

John Allgair, Victor Boksha, Benjamin Bunday, Alain Diebold, Daniel Cole, Mark Davidson, Jerry Hutcheson, Andrew Gurnell, David Joy, John McIntosh, Sylvain Muckenhirn, Joseph Pellegrini, Robert Larrabee, James Potzick, Andras Vladar, Nigel Smith, Alexander Starikov, Neal Sullivan, Oliver Wells

Proceedings Volume 5042, (2003) https://doi.org/10.1117/12.504320

KEYWORDS: Metrology, Diagnostics, Dimensional metrology, Optical lithography, Manufacturing, Process control, Image processing, Critical dimension metrology, Semiconducting wafers, Edge roughness

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Proceedings Article | 2 June 2003 Paper

Performance study of new segmented overlay marks for advanced wafer processing

Mike Adel, John Allgair, David Benoit, Mark Ghinovker, Elyakim Kassel, C. Nelson, John Robinson, Gary Seligman

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483477

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Optical design, Data modeling, Lithography, Metals, Image segmentation, Optical lithography, Imaging metrology

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Proceedings Article | 22 August 2001 Paper

Characterization of optical proximity correction features

John Allgair, Michelle Ivy, Kevin Lucas, John Sturtevant, Richard Elliott, Chris Mack, Craig MacNaughton, John Miller, Mike Pochkowski, Moshe Preil, John Robinson, Frank Santos

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436743

KEYWORDS: Optical proximity correction, Reticles, Photomasks, Lithography, Scanning electron microscopy, Critical dimension metrology, Etching, Semiconducting wafers, Tolerancing, Optical lithography

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Proceedings Article | 22 August 2001 Paper

Implementation of spectroscopic critical dimension (SCD) (TM) for gate CD control and stepper characterization

John Allgair, David Benoit, Mark Drew, Robert Hershey, Lloyd Litt, Pedro Herrera, Umar Whitney, Marco Guevremont, Ady Levy, Suresh Lakkapragada

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436771

KEYWORDS: Single crystal X-ray diffraction, Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Process control, Spectroscopy, Spectroscopes, Metrology, Precision measurement, Control systems

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Proceedings Article | 18 August 2000 Paper

Benchmarking of advanced CD-SEMs against a new unified specification for sub-0.18-um lithography

Alain Deleporte, John Allgair, Charles Archie, G. Banke, Michael Postek, Jerry Schlesinger, Andras Vladar, Arnold Yanof

Proceedings Volume 4181, (2000) https://doi.org/10.1117/12.395750

KEYWORDS: Lithography, Standards development, Scanning electron microscopy, Electron microscopes

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Proceedings Article | 2 June 2000 Paper

Comparison of ANOVA and Latin square measurement system analysis techniques

John Allgair

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386540

KEYWORDS: Contamination, Scanning electron microscopy, Critical dimension metrology, Process control, Metrology, Sputter deposition, Control systems, Semiconductors, Photoresist processing, Photoresist materials

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Proceedings Article | 2 June 2000 Paper

Feature integrity monitoring for process control using a CD SEM

John Allgair, Gong Chen, Stephen Marples, David Goodstein, John Miller, Frank Santos

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386475

KEYWORDS: Etching, Process control, Line scan image sensors, Critical dimension metrology, Image processing, Inspection, Scanning electron microscopy, Image analysis, Image quality, Cadmium

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Proceedings Article | 2 June 2000 Paper

Manufacturing considerations for implementation of scatterometry for process monitoring

John Allgair, David Benoit, Robert Hershey, Lloyd Litt, Ibrahim Abdulhalim, William Braymer, Michael Faeyrman, John Robinson, Umar Whitney, Yiping Xu, Piotr Zalicki, Joel Seligson

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386465

KEYWORDS: Scatterometry, Reflectivity, Scanning electron microscopy, Critical dimension metrology, Metrology, Silicon, Atomic force microscopy, Manufacturing, Process control, Semiconducting wafers

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Proceedings Article | 2 June 2000 Paper

Benchmarking of advanced CD-SEMs against the new unified specification for sub-0.18-um lithography

Alain Deleporte, John Allgair, Charles Archie, G. Banke, Michael Postek, Jerry Schlesinger, Andras Vladar, Arnold Yanof

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386524

KEYWORDS: Semiconducting wafers, Scanning electron microscopy, Metrology, Atomic force microscopy, Wafer testing, Contamination, Manufacturing, Critical dimension metrology, Lithography, Standards development

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The Advanced Metrology Advisory Group (AMAG) comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). (Allgair, et al., 1998) This paper describes the results of an effort to benchmark six CD-SEM instruments according to this specification. The consensus among the AMAG metrologists was that many critical areas of performance of CD-SEMs required improvement. Following this assessment this specification for benchmarking was developed. The advanced CD-SEM specification addresses several critical areas for improvement, each with its own a separate section. The critical areas covered are: precision, accuracy, charging and contamination, performance matching, pattern recognition and stage navigation accuracy, throughput, and instrumentation outputs. Each section of the specification contains a concise definition of the respective performance parameter, and wherever appropriate refers to ISO definitions. The test methodology is described, complete with the relevant statistical analysis. Many parameters (including precision, matching, and magnification accuracy) are numerically specified to be consistent with the International Technology Roadmap for Semiconductors (ITRS, 1999). Other parameters, such as charging and linewidth accuracy, are targeted with guidelines for improvement. The test wafers developed for determining the level of compliance with the specification are also discussed. The AMAG circulated this report among the metrology instrument suppliers and conferred with them. Certain components of the specification have already been adopted by some of the manufacturers in their newer metrology instruments. International SEMATECH fabricated the AMAG test wafers described herein. Measurements on six state-of-the-art metrology instruments using the AMAG test wafers have been carried out and the results were processed according to this specification. A review of the results is presented in this paper.

Proceedings Article | 26 July 1999 Paper

Characterization of CD control for sub-0.18-um lithographic patterning

John Sturtevant, John Allgair, Chong-Cheng Fu, Kent Green, Robert Hershey, Michael Kling, Lloyd Litt, Kevin Lucas, Bernard Roman, Gary Seligman, Mike Schippers

Proceedings Volume 3679, (1999) https://doi.org/10.1117/12.354335

KEYWORDS: Critical dimension metrology, Error analysis, Optical lithography, Semiconducting wafers, Reticles, Metrology, Deep ultraviolet, Lithography, Reflectivity, Resistance

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Proceedings Article | 14 June 1999 Paper

Characterization of overlay tolerance requirements for via to metal alignment

John Allgair, Mike Schippers, Brad Smith, Richard Elliott, John Miller, John Robinson

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350811

KEYWORDS: Oxides, Overlay metrology, Scanning electron microscopy, Critical dimension metrology, Tolerancing, Copper, Metals, Electrical breakdown, Optical alignment, Resistance

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Proceedings Article | 8 June 1998 Paper

SPC tracking and run monitoring of a CD SEM

John Allgair, Dustin Ruehle, Richard Elliott, Pedro Herrera, John Miller

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308732

KEYWORDS: Critical dimension metrology, Line scan image sensors, Scanning electron microscopy, Semiconducting wafers, Manufacturing, Contamination, Diagnostics, Time metrology, Calibration, Semiconductor manufacturing

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Proceedings Article | 8 June 1998 Paper

Toward a unified advanced CD-SEM specification for sub-0.18-um technology

John Allgair, Charles Archie, G. Banke, E. Hal Bogardus, Joseph Griffith, Herschel Marchman, Michael Postek, Lumdas Saraf, Jerry Schlesinger, Bhanwar Singh, Neal Sullivan, Lee Trimble, Andras Vladar, Arnold Yanof

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308724

KEYWORDS: Semiconducting wafers, Metrology, Pattern recognition, Scanning electron microscopy, Contamination, Lithography, Calibration, Standards development, Wafer testing, Electron microscopes

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Proceedings Article | 7 July 1997 Paper

Alternative method for monitoring an in-line CD SEM

Pedro Herrera, Susan Dick, John Allgair

Proceedings Volume 3050, (1997) https://doi.org/10.1117/12.275948

KEYWORDS: Semiconducting wafers, Scanning electron microscopy, Critical dimension metrology, Contamination, Manufacturing, Semiconductor manufacturing, Semiconductors, Electron microscopes, Process control, Imaging systems

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Proceedings Article | 7 July 1997 Paper

Full-field CD control for sub-0.20-um patterning

John Sturtevant, John Allgair, Mark Barrick, Chong-Cheng Fu, Kent Green, Robert Hershey, Lloyd Litt, John Maltabes, Carla Nelson-Thomas, Bernard Roman, John Singelyn

Proceedings Volume 3051, (1997) https://doi.org/10.1117/12.276024

KEYWORDS: Critical dimension metrology, Deep ultraviolet, Optical lithography, Lithography, Resistance, Manufacturing, Logic

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Showing 5 of 52 publications

Proceedings Volume Editor (8)

SPIE Conference Volume | 26 August 2010

Instrumentation, Metrology, and Standards for Nanomanufacturing IV

SPIE Conference Volume | 20 August 2009

Instrumentation, Metrology, and Standards for Nanomanufacturing III

SPIE Conference Volume | 14 April 2009

Metrology, Inspection, and Process Control for Microlithography XXIII

SPIE Conference Volume | 28 August 2008

Instrumentation, Metrology, and Standards for Nanomanufacturing II

SPIE Conference Volume | 28 April 2008

Metrology, Inspection, and Process Control for Microlithography XXII

Showing 5 of 8 publications

Conference Committee Involvement (28)

Metrology, Inspection, and Process Control XXXIX

24 February 2025 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVIII

26 February 2024 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVII

27 February 2023 | San Jose, California, United States

Metrology, Inspection, and Process Control XXXVI

25 April 2022 | San Jose, California, United States

Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV

22 February 2021 | Online Only, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXIV

24 February 2020 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXIII

25 February 2019 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXII

26 February 2018 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXXI

27 February 2017 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXX

22 February 2016 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXIX

23 February 2015 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXVIII

24 February 2014 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXVII

25 February 2013 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XXVI

13 February 2012 | San Jose, California, United States

Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors V

24 August 2011 | San Diego, California, United States

Metrology, Inspection, and Process Control for Microlithography XXV

28 February 2011 | San Jose, California, United States

Instrumentation, Metrology, and Standards for Nanomanufacturing IV

2 August 2010 | San Diego, California, United States

Metrology, Inspection, and Process Control for Microlithography XXIV

22 February 2010 | San Jose, California, United States

Instrumentation, Metrology, and Standards for Nanomanufacturing III

4 August 2009 | San Diego, California, United States

Metrology, Inspection, and Process Control for Microlithography XXIII

23 February 2009 | San Jose, California, United States

Instrumentation, Metrology, and Standards for Nanomanufacturing II

10 August 2008 | San Diego, California, United States

Metrology, Inspection, and Process Control for Microlithography XXII

25 February 2008 | San Jose, California, United States

Instrumentation, Metrology, and Standards for Nanomanufacturing

29 August 2007 | San Diego, California, United States

Metrology, Inspection, and Process Control for Microlithography XXI

26 February 2007 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XX

20 February 2006 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XIX

28 February 2005 | San Jose, California, United States

Metrology, Inspection, and Process Control for Microlithography XVIII

23 February 2004 | Santa Clara, California, United States

Metrology, Inspection, and Process Control for Microlithography XVII

24 February 2003 | Santa Clara, California, United States

Showing 5 of 28 Conference Committees

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