Double patterning is one of the enabling techniques to allow for further shrinking of
devices in the future. Many different solutions, like LELE (Litho-Etch-Litho-Etch) and
LPL (Litho-Process-Litho), have been investigated in the past years. In this paper a simplified - "Litho-Cluster-Only" - solution for double patterning is presented. This topcoat-less thermal freeze process has high capability of reaching 26 nm 1:1 LS. In addition it is shown that defect counts for the thermal freeze process approach defect numbers for high end immersion processes.
This is the study report about post-develop defect on EUV resist. The resolution, sensitivity, LWR, etc. of EUV resist
have been currently studied in the development phase. We have acknowledged that resist generates a lot of defects in its
transition from i-line, KrF, ArF and immersion-ArF. However, those were just a couple of defect types in the transition,
and they were eliminated through resist improvement.
In this study, we confirmed EUV defect type using EUV exposure tool. We also evaluate defect generation using tetrabutyl-
ammonium-hydroxide (TBAH) developer. We finally discuss on the difference of defect between using KrF and
EUV exposure tool, furthermore difference of defect between using TMAH and TBAH developer.
In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To
achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled
film edge position and good uniformity around the wafer circumference is needed.
We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The
performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse
system has a good controllability of film edge position and good uniformity around the wafer circumference. The results
indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and
substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to
provide a suitable film stacking architecture for immersion lithography mass production process.
Demand for Immersion topcoat-less resist processes is being driven by the desire to reduce the cost per wafer pass.
Two key characteristics, required by high speed immersion scanners, of topcoat-less resist are high receding contact
angle and low leaching rates. The extremely hydrophobic surface required by the scanner provides significant
challenges to the remaining processing steps, especially (developer) process related defects: pattern collapse and
hydrophobic residuals. Recent developments in materials and processing techniques have led to very promising results.
In this paper the following will be presented:
Defectivity results on 45nm L/S of several topcoat-less resists, including the effects of optimized track rinse
recipes.
Results of a fundamental study on static contact angles changes of different topcoat-less resists after each
track process step to identify where in the process issues originate.
Imaging and defectivity results of 38nm L/S using the topcoat-less champion resist are presented. These
results illustrate the capability of the ASML TWINSCAN XT:1900i / Sokudo RF3i litho cluster of printing
38 nm L/S in a single exposure .
In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the
architecture will restrict lithographic area within a wafer due to top side EBR accuracy
In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study
used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This
evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge.
Patterning defects were improved with suitable film stacking.
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