This will count as one of your downloads.
You will have access to both the presentation and article (if available).
This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.
Advanced computational methods such as ILT and model-based SRAF optimization are well known to have considerable benefits in process window and resolution for low-K1 193 lithography. However, these methods have not been well studied to understand their benefits for lower-K1 EUV lithography where fabs must push EUV resolution, 2D accuracy and process window to their limits. In this paper, we investigate where inverse lithography methods can improve EUV patterning weaknesses vs. traditional OPC/RET. We first show how ILT can be used to guide a better understanding of optimal solutions for EUV mask synthesis. We then provide detailed comparisons of ILT and traditional methods on a wide range of mask synthesis applications.
However, OPC/RET requirements at each node have changed radically in the last 20 years beyond just technical requirements. The volume of engineering work to be done has also skyrocketed. The number of device layers which need OPC/RET can be 10X higher than in earlier nodes. Additionally, the number of mask layers per device layer is often 2X or more times higher with multiple patterning. Finally, the number of features to correct per mask increases ~2X with each node. These factors led to a large increase in the number of OPC engineers needed to develop the complex new OPC/RET recipes for advanced nodes.
In this paper, we describe new developments which significantly improve the productivity of OPC engineers to deploy Rule Based OPC (RBOPC), Model Based OPC (MBOPC), AF, and ILT recipes in modern manufacturing flows. In addition to technical improvements such as novel multiple segment hotspot fixing solvers and ILT hot-spot fixing necessary to support correction needs, we have re-architected the entire flow based on how OPC engineers now develop and maintain OPC/RET recipes. The re-architecture of the flow takes advantages of more recent developments in modular and structured programming methods which are known to benefit ease engineering software development applications. Therefore, this improved OPC/RET development methodology includes specifically targeted advanced new technical functions; new types of modular structures for much faster reuse of customizations; and new interfaces to flexible programming capabilities to enable easier development and integration of deep customizations for the most challenging technical needs.
Optical proximity correction (OPC) is now a requirement for advanced semiconductor manufacturing. OPC alters the designed layout to compensate for systematic patterning distortions and/or to implement process latitude improving methods. Accurate and practical model-based OPC implementation is needed with essentially all lithography resolution enhancement techniques (RET) on complex real world designs. This practical example-oriented class will prepare attendees to implement manufacturable rule and model-based OPC on their product designs and introduce them to optimized OPC, design & process solution methods known as lithographic Design for Manufacturability (DFM).
Optical proximity correction (OPC) and reticle enhancement techniques (RET) are fundamental requirements for advanced semiconductor manufacturing. OPC is a class of techniques which alter the design layout in order to: compensate for systematic patterning distortions; implement process latitude improving methods (i.e., RET); and verify mask pattern correctness. Accurate and practical rule-based or model-based OPC methods are needed to correctly implement essentially all advanced lithography extensions (e.g., sub-resolution assist features, double patterning, EUV) on complex real world designs. This practical example-oriented class will help prepare attendees to understand, implement and validate manufacturable rule and model-based OPC on their product designs.
View contact details
No SPIE Account? Create one
