We present the progress of NEBULA project that is targeting the development of BTO based plasmonic modulators in the O- and C- bands and a Neuro Augmented C-band Coherent Receiver.
Integrated tunable lasers based on the co-integration of InP-based SOAs with low-loss Si3N4 dielectric waveguides have emerged as promising solutions in applications where the control of light phase is fundamental. Μicrowave photonics, coherent communications and LIDARs are only some of the applications where sub-KHz linewidths have already been achieved. Nevertheless, the majority of these demonstrations are based on Si3N4 platforms featuring thicknesses lower than 300nm and providing modes with effective indices below 1.6 imposing a major restriction on the achievable FSR values and devices’ footprint. In this work, we present the design of Vernier ring-inspired reflectors based on an 800nm- thick Si3N4 platform providing a TE fundamental mode with an effective index close to 1.71 for a width of 800nm, a group index close to 2.08 at λ=1550nm wavelength, and propagation losses as low as 0.2dB/cm. The proposed thick- Si3N4 designs are based on a simple dual ring Vernier configuration achieving an experimental FSR near 38nm and a 15dB side-mode suppression. These results are in close agreement with the ones obtained theoretically through a detailed Transfer Matrix Formulation verifying the accuracy of the presented semi-analytical model. This simulation model is then employed for the prediction of the performance of more advanced structures such as triple cascaded and high-order Vernier Ring designs, towards extending the achievable FSR and SMSR metrics.
In this work, we present the design process and experimental evaluation of a 1×2 asymmetric power splitters based on the self-imaging principle that is applied on an ultra-low-loss 800nm thick Si3N4 platform. The asymmetry in the multimode interference region is induced by removing a rectangular piece from the edge of the coupler, prompting a disruption at the interference pattern and adjusting accordingly the splitting power ratio. The design of the MMIs operating in the 1500- 1600nm wavelength region was realized through 3D-FDTD calculation method and the experimental results agree with theory providing an error of 5% in splitting ratio and less than -0.6dB insertion losses.
The ever-increasing energy consumption of Data Centers (DC), along with the significant waste of resources that is observed in traditional DCs, have forced DC operators to invest in solutions that will considerably improve energy efficiency. In this context, Rack- and board-scale resource disaggregation is under heavy research, as a groundbreaking innovation that could amortize the energy and cost impact caused by the vast diversity in resource demand of emerging DC workloads. However disaggregation, by breaking apart the critical CPU-to-memory path, introduces a challenging set of requirements in the underlying network infrastructure, that has to support low-latency and high-throughput communication for a high number of nodes.
In this paper we present our recent work on optical interconnects towards enabling resource disaggregation both on Rack-level as well as on board-level. To this end, we have demonstrated the Hipoλaos architecture that can efficiently integrate Spanke-based switching with AWGR-based wavelength routing and optical feedforward buffering into highport switch layouts. The proof-of-concept Hipoλaos prototype, based on the 1024-port layout, provide latency performance of 456ns, while system level evaluations reveal sub-μs latency performance for a variety of synthetic traffic profiles. Moving towards high-capacity board-level interconnects, we present the latest achievements realized within the context of H2020-STREAMS project, where single-mode optical PCBs hosting Si-based routing modules and mid-board optics are exploited towards a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s throughput. Finally, we combine the Hipolaos and STREAMS architectures in a dual-layer switching scheme and evaluate its performance via system-level simulations.
The integration of optical sources in Si photonic transceivers has relied so far on externally coupled III-V laser dies within the assembly. These hybrid approaches are however complex and expensive, as there are additional cost-increasing factors coming from the redundant testing of the pre- and post-coupled laser photonic chips. Further optimization of Photonic Integrated Circuits (PICs) cost and performance can be obtained only with radical technology advancements, such as the “holy grail” of Silicon Photonics; the monolithic integration of III-V sources on Si substrates. MOICANA project funded by EU Horizon 2020 framework targets to develop the technological background for the epitaxy of InP Quantum Dots directly on Si by Selective Area Growth with the best-in-class, in terms of losses and temperature sensitivity, in a CMOS fab, i.e. the SiN waveguide technology. In addition, MOICANA will develop the necessary interface for the seamless light transition between the III-V active and the SiN passive part of the circuitry featuring advanced multiplexing functionality and a combination of efficient and broadband fiber coupling. Through this unique platform, MOICANA aims to demonstrate low cost, inherent cooler-less and energy efficient transmitters, attributes stemming directly from the low loss SiN waveguide technology and the QD nature of the laser’s active region. MOICANA is targeting to exploit the advantages of the monolithic integrated PICs for the demonstration of large volume single-channel and WDM transmitter modules for data center interconnects, 5G mobile fronthaul and coherent communication applications.
Silicon photonics technology has demonstrated, over the years, Photonic Integrated Circuits (PICs) relying on Si or Si3N4 materials that feature advanced functionalities for a wide area of applications. However, the fabrication of such PICs is usually compatible only with Front-End-of-Line (FEOL) processes that render very difficult post processing of the involved chips towards providing efficient interfaces with optical sources. This is a major problem for the next generation photonic circuits that are expected to co-integrate III-V laser sources on the Si substrate in a monolithic way, as the coupling interface between the active and the passive part of the PIC should be developed after the epitaxy and the fabrication of the lasers. In this work, we report on the development of a novel Silicon Rich Nitride (SRN) material with low stress and high refractive index (n<3.16), close to that of InP and InGaAsP which are commonly utilized for the laser sources. The SRN has been characterized with spectroscopic ellipsometry and Fourier-Transform Infrared Spectroscopy for estimation of complex refractive index and hydrogen content in the film. Based on this material, a trilayer stack has been developed for the formation of waveguides compatible with the Back-End-of-Line (BEOL) processes, while propagation losses have been extracted through cut-back measurements. These experimental results were then inserted as input parameters in 2D- and 3D-FDTD simulations for the design of efficient interfaces between III-V lasers and Si3N4 waveguides providing coupling efficiencies that can reach 83.81% and back-reflections of 0.032%.
Silicon photonics technology has emerged as a viable solution for the demonstration of highly functional Photonic Integrated Circuits (PICs) relying on the mixture of light sources with silicon based waveguides. However, the incorporation of the laser sources in all PICs has always been at the center of industrial and research attention. To date, the vast majority of such merging schemes focus on either flip chip bonding of external III-V dies or hybrid-integration techniques that feature very good optical performance at the expense of fabrication cost. The next evolution of PICs, however will rely on the monolithic integration of the III-V lasers on the silicon substrates for simultaneous optimization of cost and circuit performance. In this work two low-loss coupling interface schemes are presented for efficient light transition between monolithically integrated InP-based laser sources and a Si3N4 passive circuitry through an intermediate waveguiding layer. For both coupling interface schemes, the light is butt-coupled from the III-V source into an intermediate waveguide that in turn couples the light into the final Si3N4 waveguide platform utilizing an evanescent coupling scheme. Two approaches are investigated towards this direction: The first approach is based on a purely stoichiometric Si3N4 waveguide, while the second one is based on a Si-Rich Nitride (SRN) acting as the intermediate layer. In both cases 2D-FDTD simulations verified by 3D-FDTD simulation results reveal total transition losses of less than 1.7dB for the pure-Si3N4 and less than 1dB for the SRN approach.
KEYWORDS: Eye, Signal attenuation, Signal processing, Data conversion, Modulators, Optical filters, Bandpass filters, Amplitude modulation, Information science, Network architectures
The 5G-induced paradigm shift from traditional macro-cell networks towards ultra-dense deployment of small cells, imposes stringent bandwidth and latency requirements in the underlying network infrastructure. While state of the art TDM-PON e.g. 10G-EPON, have already transformed the fronthaul networks from circuit switched point-to-point links into packet based architectures of shared point-to-multipoint links, the 5G Ethernet-based fronthaul brings new requirements in terms of latency for an inherently bursty traffic. This is expected to promote the deployment of a whole new class of optical devices that can perform with burst-mode traffic while realizing routing functionalities at a low-latency and energy envelope, avoiding in this way the latency burden associated with a complete optoelectronic Ethernet routing process and acting as a fast optical gateway for ultra-low latency requiring signals. Wavelength conversion can offer a reliable option for ultra-fast routing in access and fronthaul networks, provided, however, that it can at the same time offer both packet power-level equalization to account for differences in optical path losses and comply with the typical, in optical fronthauling, NRZ format. In this paper, we demonstrate an optical Burst-Mode Wavelength Converter using a Differentially-Biased SOA-MZI that operates in the deeply saturated regime to provide optical output power equalization for different input signal powers. The device has been experimentally validated for 10Gb/s NRZ optical packets, providing error-free operation for an input packet peak-power dynamic range of more than 9dB.
KEYWORDS: Switches, Optical switching, Field programmable gate arrays, Data centers, Switching, Computer architecture, Signal processing, Modulation, Device simulation, Data conversion
Disaggregated Data Centers (DCs) have emerged as a powerful architectural framework towards increasing resource utilization and system power efficiency, requiring, however, a networking infrastructure that can ensure low-latency and high-bandwidth connectivity between a high-number of interconnected nodes. This reality has been the driving force towards high-port count and low-latency optical switching platforms, with recent efforts concluding that the use of distributed control architectures as offered by Broadcast-and-Select (BS) layouts can lead to sub-μsec latencies. However, almost all high-port count optical switch designs proposed so far rely either on electronic buffering and associated SerDes circuitry for resolving contention or on buffer-less designs with packet drop and re-transmit procedures, unavoidably increasing latency or limiting throughput. In this article, we demonstrate a 256x256 optical switch architecture for disaggregated DCs that employs small-size optical delay line buffering in a distributed control scheme, exploiting FPGA-based header processing over a hybrid BS/Wavelength routing topology that is implemented by a 16x16 BS design and a 16x16 AWGR. Simulation-based performance analysis reveals that even the use of a 2- packet optical buffer can yield <620nsec latency with >85% throughput for up to 100% loads. The switch has been experimentally validated with 10Gb/s optical data packets using 1:16 optical splitting and a SOA-MZI wavelength converter (WC) along with fiber delay lines for the 2-packet buffer implementation at every BS outgoing port, followed by an additional SOA-MZI tunable WC and the 16x16 AWGR. Error-free performance in all different switch input/output combinations has been obtained with a power penalty of <2.5dB.
The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.
Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling roadmap of intra-DC optical solutions is already a reality for rack-to-rack interconnects, with recent research reporting on interesting applications of programmable silicon photonic switching fabrics addressing board-to-board and even on-board applications. In this perspective, simplified information addressing schemes like Bloom filter (BF)-based labels emerge as a highly promising solution for ensuring rapid switch reconfiguration, following quickly the changes enforced in network size, network topology or even in content location. The benefits of BF-based forwarding have been so far successfully demonstrated in the Information-Centric Network (ICN) paradigm, while theoretical studies have also revealed the energy consumption and speed advantages when applied in DCs. In this paper we present for the first time a programmable 4x4 Silicon Photonic switch that supports SDN through the use of BF-labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, allowing for its remote control through modifications in the assigned BF labels. We demonstrate 1x4 switch operation controlling the Si-Pho switch by a Stratix V FPGA module, which is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled outgoing port. DAC- and amplifier-less control of the carrier-injection Si-Pho switches is demonstrated, revealing successful switching of 10Gb/s data packets with BF-based forwarding information changes taking place at a time-scale that equals the duration of four consecutive packets.
Long and yet compact spiral waveguides based on micron-scale silicon strip waveguides has been enabled very recently by the introduction of the Euler bends. By ensuring effective broadband single mode operation of otherwise highly multimodal waveguides, these bends can have very low losses (<0.01 dB/90°) even with effective radii of a few microns. Together with the low propagation losses (< 0.15 dB/cm) of micron-scale strip waveguides, these bends enable centimeter-long delay lines with negligible losses and very small foot-print (< 1 mm2). In particular, interferometers delayed by ≈ 1 cm long spirals on one of the two arms have been fabricated on SOI wafers with both 3 um- and 4 umthick silicon layer, based on the well assessed process developed by VTT. The full devices have footprint smaller than 1.5 mm2, and they have been measured to have extinction ratios < 15 dB (reaching up to 21 dB) and about 3 dB excess losses. Functional characterization of the delayed interferometers at about 10 Gbps through demodulation of pseudorandom Differential Phase Shift Keying signals led to clearly opened eye diagrams with Q factor of 8.6 and bit error rates lower than 10-15.
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
Photonic routers are expected to enable ultra-high bit rates, high levels of integration and power efficiency. The BOOM
European project aims to develop on a SOI platform the photonic bricks towards the first silicon-optics switch fabric.
Surface plasmons polaritons are electromagnetic waves propagating along the surface of a conductor. Surface plasmons photonics is a promising candidate to satisfy the constraints of miniaturization of optical interconnects. This contribution reviews an experimental parametric study of dielectric loaded surface plasmon waveguides ring resonators and add-drop filters within the perspective of the recently suggested hybrid technology merging plasmonic and silicon photonics on a single board (European FP7 project PLATON "Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects"). Conclusions relevant for dielectric loaded surface plasmon switches to be integrated in silicon photonic circuitry will be drawn. They rely on the opportunity offered by plasmonic circuitry to carry optical signals and electric currents through the same thin metal circuitry. The heating of the dielectric loading by the electric current enables to design low foot-print thermo-optical switches driving the optical signal flow.
The European BOOM project aims at the realization of high-capacity photonic routers using the silicon material as the
base for functional and cost-effective integration. Here we present the design, fabrication and testing of the first BOOMgeneration
of hybrid integrated silicon photonic devices that implement key photonic routing functionalities. Ultra-fast
all-optical wavelength converters and micro-ring resonator UDWDM label photodetectors are realized using either 4um
SOI rib or SOI nanowire boards. For the realization of these devices, flip-chip compatible non-linear SOAs and
evanescent PIN detectors have been designed and fabricated. These active components are integrated on the SOI boards
using high precision flip-chip mounting and heterogeneous InP-to-silicon integration techniques. This type of scalable
and cost-effective silicon-based component fabrication opens up the possibility for the realization of chip-scale, power
efficient, Tb/s capacity photonic routers.
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