Nanolithography processes, equipment, and software ,
Design for manufacturability and variability of nanometer IC ,
Nanoscale detection and servo systems ,
Multiobjective robust optimal control ,
System identification ,
Convex optimization and its engineering applications
In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.
In modern digital integrated-circuit designs, standard-cell libraries are key foundations. The increased leakage current, complicated design rules, and restrictive layout space make the task of designing standard cells meeting both electrical characteristic requirements and layout constraints a significant challenge. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. In this work, as a refinement of the existing approaches, a new method is proposed to find suitable initial values and reduce the electric characteristics deviation. Preliminary results indicate that the proposed method can be effective in 20-nm-grade standard-cell optimization.
Our work presents and investigates the effectiveness of a model-based proximity effect correction method for helium ion beam lithography (HIBL). This method iteratively modulates the shape of a pattern by a feedback compensation mechanism until the simulated patterning fidelity satisfies specific constraints. A point spread function (PSF) is utilized to account for all phenomena involved during the scattering events of incident ion beam particles in the resist. Patterning prediction for subsequent correction process is derived from the energy intensity distribution due to convolution between the PSF and the pattern, with an adequate cut-off threshold. The performance of this method for HIBL is examined through several designed layouts from 15- to 5-nm in half pitches, under specific process parameters, including acceleration voltage, resist thickness, and resist sensitivity. Preliminary results show its effectiveness in improving the patterning fidelity of HIBL.
In subwavelength lithography, printed patterns on the silicon wafer suffer from geometric distortions and differ from the original design. These nonrectangular patterns can seriously affect electrical characteristics and circuit performances. We extend the verification of location-dependent weighting method and further propose three single equivalent gate length (EGL) extraction methods for representing each nonrectangular gate (NRG) transistor with a single EGL model. These methods are applied to sub-20-nm fully depleted silicon on insulator (FDSOI) circuits to predict the postlithography performances. An in-house extreme ultraviolet lithography simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct three-dimensional nonrectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods is verified with TCAD circuit simulations. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the EGLs extracted from off-state only data, and from data lumping both off- and on-states, respectively, can each predict SRAM electrical characteristics with overall error <1 % , or a factor of 5 accuracy improvement over the EGLs extracted without the weightings. These methods could be used to simulate large-scale sub-20-nm FDSOI circuits with NRG transistors caused by nonideal optical effects.
The availability of metrology solutions, one of the critical factors to drive leading-edge semiconductor devices and processes, has been confronted with difficulties in advanced nodes. For developing new metrology solutions, high-quality test structures fabricated at specific sizes are needed. Electron-beam direct-write lithography has been utilized to manufacture such samples. However, it can encounter significant-resolution difficulties and may require complicated process optimization in sub-10-nm nodes. Therefore, we investigate the feasibility and patterning control of metrology test structures fabricated by helium ion beam (HIB) direct milling and HIB direct-write lithography, where HIB has the sub-nm resolution in nature. Results show that features down to 5 nm are resolvable without any resolution enhancement technique by HIB direct milling. For HIB direct-write lithography, features down to International Roadmap for Devices and Systems 1.5-nm node are also resolvable without optimization from the lithography simulation. Furthermore, patterns beyond the 1.5-nm node can be achievable with the help of the proximity effect correction technique. Preliminary results demonstrate that HIB direct milling and HIB direct-write lithography can be a promising alternative for fabricating pit-type programmed defects (PDs) and bump-type PDs, respectively. In conclusion, HIB is suggested to be a potential tool to fabricated test structures for developing advanced metrology solutions in sub-7-nm nodes.
The availability of metrology solutions, one of the critical factors to drive leading-edge semiconductor devices and processes, can be confronted with difficulties in the advanced nodes. For developing new metrology solutions, highquality test structures fabricated at specific sizes are needed. Electron-beam direct-write lithography has been utilized to manufacture such samples. However, it can encounter significant-resolution difficulties and require complicated process optimization in sub-10-nm nodes. This study investigates the feasibility and patterning control of metrology test structure fabrication by helium-ion-beam direct-write lithography (HIBDWL). Features down to IRDS 1.5-nm node are resolvable without needing any resolution enhancement technique from the lithography simulation. Further, patterns beyond 1.5-nm node can be achievable with the help of proximity effect correction technique. Preliminary results of simulation demonstrate that HIBDWL can be a promising alternative for fabricating programmed defects (PDs) and test structure to develop advanced metrology solutions in sub-7-nm nodes.
In subwavelength lithography, the printed patterns on the silicon wafer suffer from geometric distortions and different from the original design. These non-rectangular patterns can affect electrical characteristics and circuit performances seriously. In this work, we extend the verification of location-dependent weighting method and further propose three single conventional equivalent gate length (EGL) extraction methods for representing each non-rectangular gate transistor with a single EGL model. These methods are applied to sub-20nm FDSOI circuits to predict the postlithography performances. An in-house Extreme Ultraviolet Lithography (EUVL) simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct 3D non-rectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods are verified with TCAD circuit simulations. A 2D EGL circuit simulation method in TCAD is proposed instead of 3D EGL method to reduce the simulation time required. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the off-state EGL (EGLoff) with weightings is good enough. These methods could be used to simulate the non-rectangular transistors applied to sub-20nm FDSOI circuits including 6T-SRAM caused by non-ideal optical effects in industrial processes.
Model-based optical proximity correction (MPOPC) has been well adopted in subwavelength lithography for integrated-circuit manufacturing. Typical MBOPC algorithms involve with iteratively moving the layout polygon edges to reduce the edge placement errors (EPEs) predicted by the lithography model. At each iteration, the amounts of movement are mainly determined by the values of the EPEs and the correction factors (CFs). Since full-chip lithography simulation is very computation intensive, it is highly desirable to minimize the number of iterations for acceptable run times, by selecting suitable CFs. In practical applications, the CFs are usually heuristically determined and applied globally throughout the correction regions. This approach efficiently reduces the EPEs at most of the target points but the entire convergence can be hampered at a relatively small number of hot-spot locations. This work investigates the effectiveness of improving the overall convergence by introducing both global and local CFs, and approaches to utilize machine-learning techniques to estimate the hot-spot locations and associated local CF values.
This work presents a model-based proximity effect correction method and investigates its potential for helium ion beam lithography (HIBL). This method iteratively modulates the shape of pattern by a feedback compensation mechanism until the simulated patterning fidelity satisfied specific constraints. A point spread function is utilized to account for all phenomena involved during the scattering events of incident ion beam particle in the resist. Patterning prediction for subsequent correction process is derived from the energy intensity distribution, as a result of convolution between the point spread function and the pattern, with an adequate threshold. The performance of this method for HIBL is examined through several designed patterns from 15- to 5-nm HP under certain process parameters, including acceleration voltage, resist thickness and sensitivity. Preliminary results show its effectiveness on improving the patterning fidelity of HIBL.
The availability of metrology solutions, one of the key factors to drive leading edge semiconductor devices and processes, can be confronted with difficulties in the advanced node. For developing new metrology solutions, high quality test structures fabricated at specific sizes are needed. Conventional resist-based lithography have been utilized to manufacture such samples. However, it can encounter significant resolution difficulties or requiring complicated optimization process for advanced technology node. In this work, potential of helium ion beam direct milling (HIBDM) for fabricating metrology test structures with programmed imperfection is investigated. Features down to 5 nm are resolvable without implementing any optimization method. Preliminary results have demonstrated that HIBDM can be a promising alternative to fabricate metrology test structures for advanced metrology solutions in sub 10 nm node.
Accurate and fast kernel-based proximity effect correction (PEC) models are indispensable to full-chip proximity effect simulation and correction. The attempt to utilize optical scatterometers for PEC model calibration instead of scanning electron microscopes is primarily motivated by the fact that scatterometry can be faster, more stable, and more informative if carefully implemented. Conventional scatterometry measures periodic patterns and retrieves their dimensional parameters by solving inverse problems of optical scattering with predefined libraries of the periodic patterns. PEC model parameters can be subsequently calibrated with the retrieved dimensional parameters. However, measuring only periodic patterns limits the usage of scatterometry, and the dimensional reconstruction is prone to generate estimation errors for patterns with complex three-dimensional geometry. Previously, we have proposed directly utilizing scattering light for PEC model calibration without the need for the intermediate step of retrieving the dimensional parameters. By iteratively comparing scattered light from predefined calibration patterns measured by a scatterometer to that predicted by the corresponding scattering and lithography models, PEC model parameters can be effectively calibrated with standard numerical optimization algorithms and one-dimensional periodic patterns. In this work, two-dimensional periodic circuit layouts are designed and utilized to study the applicability and potential limitations of the proposed method on the lithography of practical circuit designs.
Line edge roughness (LER) influencing the electrical performance of circuit components is a key challenge for electronbeam
lithography (EBL) due to the continuous scaling of technology feature sizes. Controlling LER within an acceptable
tolerance that satisfies International Technology Roadmap for Semiconductors requirements while achieving high
throughput become a challenging issue. Although lower dosage and more-sensitive resist can be used to improve
throughput, they would result in serious LER-related problems because of increasing relative fluctuation in the incident
positions of electrons. Directed self-assembly (DSA) is a promising technique to relax LER-related pattern fidelity (PF)
requirements because of its self-healing ability, which may benefit throughput. To quantify the potential of throughput
improvement in EBL by introducing DSA for post healing, rigorous numerical methods are proposed to simultaneously
maximize throughput by adjusting writing parameters of EBL systems subject to relaxed LER-related PF requirements.
A fast, continuous model for parameter sweeping and a hybrid model for more accurate patterning prediction are
employed for the patterning simulation. The tradeoff between throughput and DSA self-healing ability is investigated.
Preliminary results indicate that significant throughput improvements are achievable at certain process conditions.
The effects of void-based photonic crystal mirrors on reflectivity and dissipation for extreme-ultraviolet (EUV) radiation at near-normal illumination are studied. The mirrors are based on a multilayer coating comprising alternating layers of molybdenum (Mo) and silicon (Si) with 40 periods. By embedding voids in silicon films instead of molybdenum films, we found that the reflectivities of the mirror are increased and the absorptions of the mirror are decreased with the increments of the voids. On the other hand, the reflectivities of the mirror are decreased and the absorptions are increased by embedding voids in the molybdenum films, with the increments of the voids. Compared to the standard designs of 40 Mo/Si multilayer mirrors, which are currently used in most EUV or soft x-ray applications, the reflectivity of the void-based photonic crystal mirror in our study can reach from 73.43 to 83.24% and the absorption can decline from 26.18 to 16.80%. In consideration of EUV bandwidth, the effects of illumination angles in the six-mirror projection system, the intermixing layers, and the variation of the coated absorber thickness on the reflection properties are studied. The proposed concept can be used in next-generation EUV lithography and soft x-ray optical systems.
KEYWORDS: Calibration, Lithography, Optical proximity correction, Data modeling, Signal processing, Scatterometry, Process control, Photomasks, Process modeling, Systems modeling
Fast and robust metrologies for retrieving large amount of accurate wafer data is the key to meet the ever stricter semiconductor manufacturing process control such as critical dimension (CD) and overlay as the industry moving towards 22 nm or smaller designs. Scatterometry emerges due to its non-destructivity and rapid availability for accurate wafer data. In this paper we simulate the ability of a new scatterometry method to show its accurate control over lithography model and OPC model calibrations. The new method directly utilizes scattering signals of scatterometry to control the process instead of using numerically analyzed dimensional parameters such as CD and side wall angle (SWA). The control can be achieved by optimizing the scattering signal of one process by tuning numerical aperture (NA), sigma, or lens aberration to match the signal of the target process. In this work only sigma is used for optimization. We found that when the signals of both processes are matched with minimized optimization error, CD of the grating profiles on the wafers are also minimized. This result enables valid lithography process control and model calibration with the new method.
KEYWORDS: Electron beam lithography, Monte Carlo methods, Line edge roughness, Computer simulations, Critical dimension metrology, Transistors, Optical simulations, Diffusion, Optimization (mathematics), Point spread functions
Low-energy electron beam lithography is one of the promising next-generation lithography technology solutions for the 21-nm half-pitch node and beyond because of fewer proximity effects, higher resist sensitivity, and less substrate damage compared with high-energy electron beam lithography. To achieve high-throughput manufacturing, low-energy electron beam lithography systems with writing parameters of larger beam size, larger grid size, and lower dosage are preferred. However, electron shot noise can significantly increase critical dimension deviation and line edge roughness. Its influence on patterning prediction accuracy becomes nonnegligible. To effectively maximize throughput while meeting patterning fidelity requirements according to the International Technology Roadmap for Semiconductors, a new method is proposed in this work that utilizes a new patterning prediction algorithm to rigorously characterize the patterning variability caused by the shot noise and a mathematical optimization algorithm to determine optimal writing parameters. The new patterning prediction algorithm can achieve a proper trade-off between computational effort and patterning prediction accuracy. Effectiveness of the new method is demonstrated on a static random-access memory circuit. The corresponding electrical performance is analyzed by using a gate-slicing technique and publicly available transistor models. Numerical results show that a significant improvement in the static noise margin can be achieved.
KEYWORDS: Calibration, Line edge roughness, Scatterometry, Point spread functions, Process modeling, Scanning electron microscopy, Metrology, Scattering, Semiconducting wafers, Cadmium
Scatterometry has been proven to be effective in critical dimension (CD) and sidewall angle (SWA) measurements with
good precision and accuracy. In order to study the effectiveness of scatterometry measurement of line edge roughness
(LER), calibration samples with known LER have to be fabricated precisely. The relationship between ITRS LER
specifications and the feature dimension design of the LER calibration samples is discussed. Electron-beam-direct-write
lithography (EBDWL) has been widely used in nanoscale fabrication and is a natural selection for fabricating the
designed calibration samples. With the increasingly demanding requirement of lithography resolution in ITRS, the
corresponding LER feature of calibration samples becomes more and more challenging to fabricate, even for EBDWL.
Proximity effects in EBDWL due to electron scattering can cause significant distortion of fabricated patterns from
designed layouts. Model-based proximity effect correction (MBPEC) is an enhancement method for EBDWL to
precisely define fine resist features. The effectiveness of MBPEC depends on the availability of accurate electron-beam
proximity effect models, which are usually described by point spread functions (PSFs). In this work, a PSF in a double-
Gaussian function form at a 50 kV accelerating voltage, an effective beam size, and a development threshold energy
level of the resist are calibrated with EBDWL exposure tests. Preliminary MBPEC results indicate its effectiveness in
calibration sample fabrication.
Optical scatterometry is crucial to advanced nodes due to its ability of non-destructively and rapidly retrieving accurate
3D profile information.1, 2, 3 In recent years, an angle-resolved polarized reflectometry-based scatterometry which can
measure critical dimensions, overlay, and focus in single shot has been developed.4, 6, 20 In principle, a microscope
objective collects diffracted light, and pupil images are collected by a detector. For its application of calibrating
lithography models, the pupil images are fit to a database pre-characterized usually by rigorous electromagnetic
simulation to estimate dimensional parameters of developed resist profiles.5 The estimated dimensional parameters can
then be used for lithography model calibration. In this work, we propose a new method which directly utilizes the pupil
images to calibrate lithography models without needing dimensional parameter estimation. To test its feasibility and
effectiveness by numerical simulation, a reference lithography process model is first constructed with a set of parameter
values complying with ITRS. A to-be-calibrated process model is initialized with a different set of parameter values from
those of the reference model. Rigorous electromagnetic simulation is used to obtain the pupil images of the developed
resist profiles predicted by both process models. An optimization algorithm iteratively reduces the difference between
the pupil images by adjusting the set of parameter values of the to-be-calibrated process model until the pupil image
difference satisfies a predefined converging criterion. This method can be used to calibrate both rigorous first-principle
models for process and equipment development and monitoring, and fast kernel-based models for full-chip proximity
effect simulation and correction. Preliminary studies with both 1D and 2D aperiodic and periodic layouts indicate that
when the pupil image difference is minimized, the lithography model can be accurately calibrated.
Electron-beam-direct-write lithography has been considered a candidate next-generation technique for achieving high resolution. An accurate point spread function (PSF) is essential for reliable patterning prediction and proximity-effects correction. It can be derived via an effective parametric PSF calibration methodology, typically involving the fitting of the absorbed energy distribution (AED) from an electron-scattering simulation. However, the existing parametric PSF calibration methodology does not employ a systematic approach to obtain a new PSF form that is both compact and accurate when conventional PSF forms are not satisfactory. Only the AED fitting quality (rather than its patterning-prediction quality) is considered during the conventional calibration methodology. It also lacks a process to consider whether the predicted deviation (as simulated using the chosen PSF form) is satisfactory. This paper proposes a new parametric PSF calibration methodology to systematically obtain a PSF form consisting of the smallest number of terms, with a better combination of basis functions and that optimizes pattern accuracy. The effectiveness of using the new methodology is demonstrated in terms of fitting accuracy, patterning-prediction accuracy, and patterning sensitivity.
As integrated circuit design dimensions continue to shrink, previously ignored three-dimensional (3-D) mask effects have become significant for the accurate prediction and correction of proximity effects. Optical proximity correction (OPC) process models must consequently take into account 3-D mask effects. The state-of-the-art model-based OPC methodology, which is called delta-chrome OPC (DCOPC), needs the repeated computation of the mask perturbation to facilitate its convergence. The increasing complexity of OPC process models challenges this DCOPC methodology because each computation of the mask perturbation becomes prohibitively expensive. In this study, a new model-based OPC methodology, which is called non-delta-chrome OPC (non-DCOPC), is proposed without introducing any mask perturbations. It only requires image intensity information to achieve convergence using classical control techniques, and its effectiveness is demonstrated, showing that the run time with and without considering 3-D mask effects can be significantly improved. In addition, the correction accuracy of the DCOPC and non-DCOPC methodologies without considering 3-D mask effects is quite comparable. However, the correction accuracy considering 3-D mask effects can be slightly improved by the non-DCOPC methodology.
Extreme ultraviolet (EUV) lithography is a promising candidate for high-volume manufacturing at the 22-nm half-pitch node and beyond. EUV projection lithography systems need to rely on reflective optical elements and masks with oblique illumination for image formation. It leads to undesired effects such as pattern shift and horizontal-to-vertical critical dimension bias, which are generally reported as shadowing. Rule-based approaches proposed to compensate for shadowing include changing mask topography, introducing mask defocus, and biasing patterns differently at different slit positions. However, the electromagnetic interaction between the incident light and the mask topography with complicated geometric patterns, such as optical diffraction, not only causes shadowing but also induces proximity effects. This phenomenon cannot be easily taken into account by rule-based corrections and thus imposes a challenge on a partially model-based correction flow, the so-called combination of rule- and model-based corrections. A fully model-based correction flow, which integrates an in-house optical proximity correction algorithm with rigorous three-dimensional mask simulation, is proposed to simultaneously compensate for shadowing and proximity effects. Simulation results for practical circuit layouts indicate that the fully model-based correction flow significantly outperforms the partially model-based one in terms of correction accuracy, while the total run time is slightly increased.
The modified transmission line theory is used to calculate equivalent refractive indices of the extreme ultraviolet (EUV) mask multilayer (ML) over wavelengths from 13.35 to 13.65 nm for finite-difference time-domain (FDTD) simulation. Generally speaking, a fine mesh requiring huge memory and computation time are necessary to get accurate results in an FDTD simulation. However, it is hard to get accurate results for ML simulation due to the thin thickness of each layer. By means of an equivalent refractive index, the ML can be treated as one layer with the bulk effective material. Using FDTD simulations, we study the reflectivities of 40 Mo/Si ML and bulk material cases. The ML structure and bulk material with periodic excessive surface roughness as well as patterned with periodic contact holes are also studied by using two- and three-dimensional FDTD simulations. The simulation cases for a single wavelength and for a full-bandwidth EUV light source with a 6 ML system are studied. The results from each simulation show that the root mean square error between ML simulations and the bulk material simulations are confined within 3.3%, and all cases indicate that the FDTD computation time of bulk material is about half as compared with a 40-ML simulation.
KEYWORDS: Semiconducting wafers, Maskless lithography, Lithography, Photomasks, Data processing, Manufacturing, Electron beams, Data centers, Lenses, Microelectromechanical systems
Electron-beam lithography is promising for future manufacturing technology because it does not suffer from wavelength
limits set by light sources. Since single electron-beam lithography systems have a common problem in throughput, a
multi-electron-beam lithography (MEBL) system should be a feasible alternative using the concept of massive
parallelism. In this paper, we evaluate the advantages and the disadvantages of different MEBL system architectures,
and propose our novel Massively Parallel MaskLess Lithography System, MPML2.
MPML2 system is targeting for cost-effective manufacturing at the 32nm node and beyond. The key structure of the
proposed system is its beamlet array cells (BACs). Hundreds of BACs are uniformly arranged over the whole wafer area
in the proposed system. Each BAC has a data processor and an array of beamlets, and each beamlet consists of an
electron-beam source, a source controller, a set of electron lenses, a blanker, a deflector, and an electron detector. These
essential parts of beamlets are integrated using MEMS technology, which increases the density of beamlets and reduces
the system cost. The data processor in the BAC processes layout information coming off-chamber and dispatches them
to the corresponding beamlet to control its ON/OFF status. High manufacturing cost of masks is saved in maskless
lithography systems, however, immense mask data are needed to be handled and transmitted. Therefore, data
compression technique is applied to reduce required transmission bandwidth. The compression algorithm is fast and
efficient so that the real-time decoder can be implemented on-chip. Consequently, the proposed MPML2 can achieve 10
wafers per hour (WPH) throughput for 300mm-wafer systems.
A model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write
lithography. It iteratively modulates layout geometry by feedback compensation until the correction error converges. The
energy intensity distribution is efficiently calculated by fast convolving the modulated layout with a point-spread
function which models electron beam shape and proximity effects primarily due to electron scattering in resist. The
effectiveness of this methodology is measured by iteration numbers required for meeting the patterning fidelity
specifications. It is examined versus process parameters including acceleration voltage and resist thickness with several
regular mask geometries and practical design layouts.
When EUV light is used to inspect mask defects, the reflective photons reveal information for both the mask structure
and the mask defects. The number of reflective photons has to be enough for generating sufficient detector signals. A
modeling technique based on Feynman path integral is utilized to calculate the number of reflective extreme-ultraviolet
(EUV) photons scattered from photomask surfaces. For a 2D semicircular silicon defect, the capability of predicting the
moving direction for each reemitting photon and the intensity of photons in different direction has been demonstrated.
Delta-chrome optical proximity correction (OPC) has been widely adopted in lithographic patterning for semiconductor
manufacturing. During the delta-chrome OPC iteration, a predetermined amount of chrome is added or subtracted from
the mask pattern. With this chrome change, the change of exposure intensity error (IE) or the change of edge placement
error (EPE) between the printed contour and the target pattern is then calculated based on standard Kirchhoff
approximation. Linear approximation is used to predict the amount of the proper chrome change to remove the
correction error. This approximation can be very fast and effective, but must be performed iteratively to capture
interactions between chrome changes. As integrated circuit (IC) design shrinks to the deep sub-wavelength regime,
previously ignored nonlinear process effects, such as three-dimensional (3D) mask effects and resist development effects,
become significant for accurate prediction and correction of proximity effects. These nonlinearities challenge the deltachrome
OPC methodology. The model response to mask pattern perturbation by linear approximation can be readily
computed but inaccurate. In fact, computation of the mask perturbation response becomes complex and expensive. A
non-delta-chrome OPC methodology with IE-based feedback compensation is proposed. It determines the amount of the
proper chrome change based on IE without intensive computation of mask perturbation response. Its effectiveness in
improving patterning fidelity and runtime is examined on a 50-nm practical circuit layout. Despite the presence and the
absence of nonlinear 3D mask effects, our results show the proposed non-delta-chrome OPC outperforms the deltachrome
one in terms of patterning fidelity and runtime. The results also demonstrate that process models with 3D mask
effects limit the use of delta-chrome OPC methodology.
KEYWORDS: Sensors, Monte Carlo methods, Electron beams, Signal detection, Lithography, Electron beam lithography, Detector arrays, Optical simulations, Semiconducting wafers, Silicon
Multiple-electron-beam-direct-write lithography is one of the promising candidates for next-generation lithography
because of its high resolution and ability of maskless operation. In order to achieve the throughput requirement for highvolume
manufacturing, miniaturized electro-optics elements are utilized in order to drive massively parallel beams
simultaneously. Electron beam drift problems can become quite serious in multiple-beam systems. Periodic recalibration
with reference markers on the wafer has been utilized in single-beam systems to achieve beam placement accuracy. This
technique becomes impractical with multiple beams. In this work, architecture of a two dimensional beam position
monitor system for multiple-electron-beam lithography is proposed. It consists of an array of miniaturized electron
detectors placed above the wafer to detect backscattered electrons. The relation between beam drift and distribution of
backscattered-electron trajectories is simulated by an in-house Monte Carlo electron-scattering simulator. Simulation
results indicate that electron beam drift may be effectively estimated from output signals of detector array with some
array signal processing to account for cross-coupling effects between beams.
The Finite-Difference Time-Domain (FDTD) method is used to study the scattering effects of extreme ultraviolet (EUV)
mask. It requires significant amounts of memory and computation time as the fine grid size is needed for simulation.
Theoretically, the accuracy can be increased as the mesh size is decreased in FDTD simulation. However, it is not easy
to get the accurate simulation results for the multilayer (ML) structures by FDTD method. The transmission line theory
is used to calculate the equivalent refractive index for EUV mask ML to simulate the ML as one layer of bulk artificial
material. The reflectivities for EUV light with the normal incidence and small-angle oblique incidence in the bulk
artificial material and EUV mask ML are simulated by FDTD method. The Fresnel's equation is used to evaluate the
numerical errors for these FDTD simulations, and the results show good agreement between them. Using the equivalent
refractive index material for EUV multilayer mask can reduce the computation time and have the accuracy with tolerable
numerical errors. The ML structure with periodic surface roughness is also studied by this method, and it shows that only
half of computation time is needed to substitute ML to a bulk equivalent refractive index material in FDTD simulations.
This proposed method can accelerate the simulations of EUV mask designs.
Extreme ultraviolet (EUV) lithography is one of the promising candidates for device manufacturing with features smaller
than 22 nm. Unlike traditional optical projection systems, EUV light needs to rely on reflective optics and masks with an
oblique incidence for image formation in photoresist. The consequence of using a reflective projection system can result
in horizontal-vertical (H-V) bias and pattern shift, which are generally referred as shadowing. Approaches proposed to
compensate for shadowing effect include changing mask topography, modifying mask focus, and biasing features along
the azimuth angle, which are all rule-based. However, the complicated electromagnetic interaction between closely
placed circuit patterns can not only induce additional optical proximity effect but also change the shadowing effect.
These detailed phenomena cannot be completely taken into account by the rule-based approaches. A fully model-based
approach, which integrates an in-house model-based optical proximity correction (OPC) algorithm with rigorous three-dimensional
(3D) EUV mask simulation, is proposed to simultaneously compensate for shadowing and optical proximity
effects with better pattern transfer fidelity and process windows. Preliminary results indicate that this fully model-based
approach outperforms rule-based ones, in terms of geometric printability under process variations.
KEYWORDS: Monte Carlo methods, Scattering, Electron beam lithography, Silicon, Data modeling, Polymethylmethacrylate, Laser scattering, Direct write lithography, Computer simulations, Backscatter
Accelerating voltage as low as 5 kV for operation of the electron-beam micro-columns as well as solving the
throughput problem is being considered for high-throughput direct-write lithography for the 22-nm half-pitch node and
beyond. The development of efficient proximity effect correction (PEC) techniques at low-voltage is essential to the
overall technology. For realization of this approach, a thorough understanding of electron scattering in solids, as well as
precise data for fitting energy intensity distribution in the resist are needed. Although electron scattering has been
intensively studied, we found that the conventional gradient based curve-fitting algorithms, merit functions, and
performance index (PI) of the quality of the fit were not a well posed procedure from simulation results. Therefore, we
proposed a new fitting procedure adopting a direct search fitting algorithm with a novel merit function. This procedure
can effectively mitigate the difficulty of conventional gradient based curve-fitting algorithm. It is less sensitive to the
choice of the trial parameters. It also avoids numerical problems and reduces fitting errors. We also proposed a new PI to
better describe the quality of the fit than the conventional chi-square PI. An interesting result from applying the proposed
procedure showed that the expression of absorbed electron energy density in 5keV cannot be well represented by
conventional multi-Gaussian models. Preliminary simulation shows that a combination of a single Gaussian and double
exponential functions can better represent low-voltage electron scattering.
Model-based Optical Proximity Correction (MBOPC) has become one of the most important resolution enhancement
technologies (RETs), which can effectively improve the image fidelity and process robustness. MBOPC is performed by
iteratively shifting the polygon edges of mask patterns until convergence requirements are achieved. In this paper, we
specifically discuss the design of feedback controllers to improve MBOPC convergence. Effective controller design rules
are derived from the OPC results of several circuit layouts. Meanwhile, resist models also significantly affect MBOPC
convergence. Two kinds of resist model have been proposed for MBOPC such as constant threshold resist model (CTRM)
and variable threshold resist model (VTRM). We propose a novel CTRM, called pattern-based optimal threshold
determination (PBOTD). By normalized mean square error (NMSE) formulation, appropriate threshold values with
minimum NMSE can be determined to improve image fidelity, and effectively decrease iterations required. The
effectiveness of applying both optimized controller and PBOTD is demonstrated on a 90-nm SRAM cell.
Critical dimension (CD) is one the most critical variable in the lithography process with the most direct impact
on the device speed and performance of integrated circuit. The development rate can have an impact on the CD
uniformity from wafer-to-wafer and within-wafer. Conventional approaches to controlling this process include
monitoring the end-point of the develop process and adjusting the development time or concentration from
wafer-to-wafer or run-to-run. This paper presents an innovative approach to control the development rate in
real-time by monitoring the photoresist thickness. Our approach uses an array of spectrometers positioned
above a programmable bakeplate to monitor the resist thickness. The develop process and post-development
bake process is integrated into one equipment. The resist thickness can be extracted from the spectrometers
data using standard optimization algorithms. With these in-situ measurements, the temperature profile of the
bakeplate is controlled in real-time by manipulating the heater power distribution using a control algorithm. We
have experimentally obtained a repeatable improvement in controlling the end-point of the develop process from
wafer-to-wafer and within wafer.
Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from
across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength
regime. The poly gate distortion affects device electrical characteristics, including drive current (Ion), leakage current
(Ioff), and threshold voltage (Vt). For circuits sensitive to layout, such as compact memory cells, electrical performances
can vary with image distortion of each transistor even after applying resolution enhancement technologies (RETs) such
as optical proximity corrections. In this paper, we demonstrate the impact of OPC settings on the performance of 6T-SRAM
cells. The printed transistor gate and active region patterns are simulated by an in-house OPC engine. The device
model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of
smaller rectangles. Consequently, Electrical performance such as static noise margin (SNM) can be obtained by
incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as
segmentation length and numbers of corrections can affect wafer image quality and electrical performance in different
ways.
An in-situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography is presented. Based on first principle thermal modeling of the thermal system, the temperature of the wafer can be estimated and controlled in real-time by monitoring the bake-plate temperature profile. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However as processes are subjected to process drifts, disturbances and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady-state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach.
A multibeam confocal inspection (MCI) beta-tool for mask blank defect detection has been developed and widely adopted at several organizations involved in the research and development of low-defect extreme ultraviolet (EUV) mask blanks. There are two important objectives of this tool development project: (1) ensuring that all printable multilayer and substrate defects are detectable at the
half-pitch 45-nm technology node and beyond and (2) enabling a metrology standard for acceptance or rejection of mask blanks before further processing such as deposition and patterning. This paper documents the technical challenges and the latest best known methods developed to (1) improve the detection sensitivity of the current MCI tool before the next-generation tool arrives and (2) quantify the detection sensitivity differences and correlate the measurement results of the same mask blank from different MCI tools. Several options are discussed and found to be effective to increase sensitivity. Tool differences are discussed and a calibration standard based on a tool detection model and a confocal imaging model is proposed. This work will result in one of the key methodologies required to ensure the yield of EUV lithography.
Critical dimension (CD) or linewidth is one the most critical variable in the lithography process with the most direct impact on the device speed and performance of integrated circuit. The absorption coefficient is one of the photoresist properties that can have an impact on the CD uniformity. The absorption coefficient determined the required exposure dose for printing the features. Hence, nonuniformity in absorption coefficient across the substrate will lead to nonuniformity in the linewidth. This paper presents an innovative approach to controlling the within wafer photoresist absorption coefficient uniformity. Previous works in the literature can only control the average uniformity of the absorption coefficient. Our approach uses an array of spectrometers positioned above a multizone bakeplate to monitor the absorption coefficient. The absorption coefficient can be extracted from the spectrometers data using standard optimization algorithms. With these in-situ measurements, the temperature profile of the bakeplate is controlled in real time by manipulating the heater power distribution using conventional proportional-integral (PI) control algorithm. We have experimentally obtained a repeatable improvement in the absorption coefficient uniformity from wafer-to-wafer and within wafer. A 50% improvement in absorption coefficient uniformity is achieved.
The ability of a confocal microscope to inspect for defects on EUVL mask blanks has been investigated both experimentally and theoretically. A model was developed to predict the image contrast of confocal microscope. Measurements were made on PSL spheres and programmed multilayer defects using a Lasertec M1350 operating with 488 nm light. The images obtained of PSL spheres on both fused silica and multilayer-coated blanks are found to be accurately predicted with the model using no adjustable parameters. Good agreement is also demonstrated for the modeling of multilayer defects. Predictions are made for the expected increase in contrast at the shorter wavelength of 266 nm. Substrate roughness contributes to the "noise" which limits the sensitivity to small defects. The contrast fluctuations due to roughness have been modeled using a simple single surface approximation. The model has been validated with measurements on substrates with varying degrees of roughness. The contribution of mask roughness to the sensitivity of a 266 nm tool is estimated.
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