Demand for Immersion topcoat-less resist processes is being driven by the desire to reduce the cost per wafer pass.
Two key characteristics, required by high speed immersion scanners, of topcoat-less resist are high receding contact
angle and low leaching rates. The extremely hydrophobic surface required by the scanner provides significant
challenges to the remaining processing steps, especially (developer) process related defects: pattern collapse and
hydrophobic residuals. Recent developments in materials and processing techniques have led to very promising results.
In this paper the following will be presented:
Defectivity results on 45nm L/S of several topcoat-less resists, including the effects of optimized track rinse
recipes.
Results of a fundamental study on static contact angles changes of different topcoat-less resists after each
track process step to identify where in the process issues originate.
Imaging and defectivity results of 38nm L/S using the topcoat-less champion resist are presented. These
results illustrate the capability of the ASML TWINSCAN XT:1900i / Sokudo RF3i litho cluster of printing
38 nm L/S in a single exposure .
Given the increasingly stringent CD requirements for double patterning at the 32nm node and beyond the question arises
as to how best to correct for CD non-uniformity at litho and etch. For example, is it best to apply a dose correction over
the wafer while keeping the PEB plate as uniform as possible, or should the dose be kept constant and PEB CD tuning
used to correct. In this work we present experimental data, obtained on a state of the art ASML XT:1900Gi and Sokudo
RF3S cluster, on both of these approaches, as well as on a combined approach utilizing both PEB CD tuning and dose
correction.
Given the increasingly stringent CD requirements for double patterning at the 32nm node and beyond, the question arises
as to how best to correct for CD non-uniformity at litho and etch. For example, is it best to apply a dose correction over
the wafer while keeping the PEB plate as uniform as possible, or should the dose be kept constant and PEB plate tuning
used to correct. In this paper we present experimental data using both of these approaches, obtained on an ASML
XT:1900Gi and Sokudo RF3S cluster.
The introduction of Immersion lithography, combined with the desire to maximize the number of potential
yielding devices per wafer, has brought wafer edge engineering to the forefront for advanced
semiconductor manufactures. Bevel cleanliness, the position accuracy of the lithography films, and quality
of the EBR cut has become more critical.
In this paper, the effectiveness of wafer track based solutions to enable state-of-art bevel schemes is
explored. This includes an integrated bevel cleaner and new bevel rinse nozzles. The bevel rinse nozzles
are used in the coating process to ensure a precise, clean film edge on or near the bevel. The bevel cleaner
is used immediately before the wafer is loaded into the scanner after the coating process. The bevel cleaner
shows promise in driving down defectivity levels, specifically printing particles, while not damaging films
on the bevel.
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