KEYWORDS: Signal to noise ratio, Electrons, Monte Carlo methods, Silicon, Image processing, Scanning electron microscopy, Sensors, Inspection, Defect inspection, Defect detection
Java Monte Carlo Simulator for Secondary Electrons (JMONSEL) simulations are used to generate expected imaging responses of chosen test cases of patterns and defects with the ability to vary parameters for beam energy, spot size, pixel size, and/or defect material and form factor. The patterns are representative of the design rules for an aggressively scaled FinFET-type design. With these simulated images and resulting shot noise, a signal-to-noise framework is developed, which relates to defect detection probabilities. Additionally, with this infrastructure, the effect of detection chain noise and frequency-dependent system response can be made, allowing for targeting of best recipe parameters for multielectron beam inspection validation experiments. Ultimately, these results should lead to insights into how such parameters will impact tool design, including necessary doses for defect detection and estimations of scanning speeds for achieving high throughput for high-volume manufacturing.
The EUV mask infrastructure is of key importance for the successful introduction of EUV lithography into volume production. In particular, for the production of defect free masks an actinic review of potential defect sites is required. ZEISS and the SUNY POLY SEMATECH EUVL Mask Infrastructure consortium started a development program for such an EUV aerial image metrology system, the AIMS EUV. In this paper, we provide measurement data on the system’s key specifications and discuss its performance and capability status.
Key enabler of the successful introduction of EUV lithography into volume production is the EUV mask
infrastructure. For the production of defect free masks, actinic review of potential defect sites to decide on the need
for repair or compensation is required. Also, the repair or compensation with the ZEISS MERiT electron beam repair
tool needs actinic verification in a closed loop mask repair solution. For the realization of actinic mask review,
ZEISS and the SEMATECH EUVL Mask Infrastructure consortium started a development program for an EUV
aerial image metrology system, the AIMSTM EUV, with realization of a prototype tool.
The development and prototype realization of the AIMSTM EUV has entered the tool calibration and qualification
phase utilizing the achieved capabilities of EUV aerial image acquisition and EUV mask handling. In this paper, we
discuss the current status of the prototype qualification and show recent measurement results.
The new device architectures and materials being introduced for sub-10nm manufacturing, combined with the complexity of multiple patterning and the need for improved hotspot detection strategies, have pushed current wafer inspection technologies to their limits. In parallel, gaps in mask inspection capability are growing as new generations of mask technologies are developed to support these sub-10nm wafer manufacturing requirements. In particular, the challenges associated with nanoimprint and extreme ultraviolet (EUV) mask inspection require new strategies that enable fast inspection at high sensitivity. The tradeoffs between sensitivity and throughput for optical and e-beam inspection are well understood. Optical inspection offers the highest throughput and is the current workhorse of the industry for both wafer and mask inspection. E-beam inspection offers the highest sensitivity but has historically lacked the throughput required for widespread adoption in the manufacturing environment. It is unlikely that continued incremental improvements to either technology will meet tomorrow’s requirements, and therefore a new inspection technology approach is required; one that combines the high-throughput performance of optical with the high-sensitivity capabilities of e-beam inspection.
To support the industry in meeting these challenges SUNY Poly SEMATECH has evaluated disruptive technologies that can meet the requirements for high volume manufacturing (HVM), for both the wafer fab [1] and the mask shop. Highspeed massively parallel e-beam defect inspection has been identified as the leading candidate for addressing the key gaps limiting today’s patterned defect inspection techniques. As of late 2014 SUNY Poly SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for defect inspection. A champion approach has been identified based on a multibeam technology from Carl Zeiss. This paper includes a discussion on the need for high-speed e-beam inspection and then provides initial imaging results from EUV masks and wafers from 61 and 91 beam demonstration systems. Progress towards high resolution and consistent intentional defect arrays (IDA) is also shown.
SEMATECH has initiated a program to develop massively-parallel electron beam defect inspection (MPEBI). Here we use JMONSEL simulations to generate expected imaging responses of chosen test cases of patterns and defects with ability to vary parameters for beam energy, spot size, pixel size, and/or defect material and form factor. The patterns are representative of the design rules for an aggressively-scaled FinFET-type design. With these simulated images and resulting shot noise, a signal-to-noise framework is developed, which relates to defect detection probabilities. Additionally, with this infrastructure the effect of detection chain noise and frequency dependent system response can be made, allowing for targeting of best recipe parameters for MPEBI validation experiments, ultimately leading to insights into how such parameters will impact MPEBI tool design, including necessary doses for defect detection and estimations of scanning speeds for achieving high throughput for HVM.
KEYWORDS: Scanning electron microscopy, Sensors, Electron beams, Signal to noise ratio, Image resolution, Semiconductors, Beam splitters, Brain, Image processing, Microscopy
Multiple electron beam SEMs enable detecting structures of few nanometer in diameter at much higher throughputs than possible with single beam electron microscopes at comparable electron probe parameters. Although recent multiple beam SEM development has already demonstrated a large speed increase1, higher throughputs are still required to match the needs of many semiconductor applications2. We demonstrate the next step in the development of multi-beam SEMs by increasing the number of beams and the current per beam. The modularity of the multi-beam concept ensures that design changes in the multi-beam SEM are minimized.
SEMATECH aims to identify and enable disruptive technologies to meet the ever-increasing demands of semiconductor high volume manufacturing (HVM). As such, a program was initiated in 2012 focused on high-speed e-beam defect inspection as a complement, and eventual successor, to bright field optical patterned defect inspection [1]. The primary goal is to enable a new technology to overcome the key gaps that are limiting modern day inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. The program specifically targets revolutionary solutions based on massively parallel e-beam technologies, as opposed to incremental improvements to existing e-beam and optical inspection platforms. Wafer inspection is the primary target, but attention is also being paid to next generation mask inspection. During the first phase of the multi-year program multiple technologies were reviewed, a down-selection was made to the top candidates, and evaluations began on proof of concept systems. A champion technology has been selected and as of late 2014 the program has begun to move into the core technology maturation phase in order to enable eventual commercialization of an HVM system. Performance data from early proof of concept systems will be shown along with roadmaps to achieving HVM performance. SEMATECH’s vision for moving from early-stage development to commercialization will be shown, including plans for development with industry leading technology providers.
KEYWORDS: Signal to noise ratio, Light scattering, Inspection, Semiconducting wafers, Defect inspection, Interference (communication), Contrast transfer function, Scanning electron microscopy, Scattering, Signal detection
SEMATECH has initiated a program to accelerate the development and commercialization of multi-electron beam based
technologies as successor for wafer defect inspection in high volume semiconductor manufacturing. This paper develops
the basic electron-optical performance requirements and establishes criteria for tool specifications. The performance
variations within a large array of electron beams must be minimal in order to maximize defect capture rates while
simultaneously minimizing false counts, so a series of experimental evaluations are described to quantify the random and
systematic variations in beam current, spot size, detector channel noise level, and defect sensitivity.
A comprehensive survey was sent to merchant and captive mask shops to gather information about the mask industry as
an objective assessment of its overall condition. 2013 marks the 12th consecutive year for this process. Historical topics
including general mask profile, mask processing, data and write time, yield and yield loss, delivery times, maintenance,
and returns were included and new topics were added. Within each category are multiple questions that result in a
detailed profile of both the business and technical status of the mask industry.
While each year’s survey includes minor updates based on feedback from past years and the need to collect additional
data on key topics, the bulk of the survey and reporting structure have remained relatively constant. A series of
improvements is being phased in beginning in 2013 to add value to a wider audience, while at the same time retaining
the historical content required for trend analyses of the traditional metrics. Additions in 2013 include topics such as top
challenges, future concerns, and additional details in key aspects of mask masking, such as the number of masks per
mask set per ground rule, minimum mask resolution shipped, and yield by ground rule. These expansions beyond the
historical topics are aimed at identifying common issues, gaps, and needs. They will also provide a better understanding
of real-life mask requirements and capabilities for comparison to the International Technology Roadmap for
Semiconductors (ITRS).
With each new generation of e-beam mask writers comes the ability to write leading edge photomasks with improved patterning performance and increased throughput. However, these cutting-edge e-beam tools are often used with older generation resists, preventing the end-user from taking full advantage of the tool’s potential. The generation gap between tool and resist will become even more apparent with the commercialization of multi-beam mask writers, which are expected to be available for pilot line use around 2015. The mask industry needs resists capable of meeting the resolution, roughness, and sensitivity requirements of these advanced tools and applications.
The E-beam Resist Test Facility (ERTF) has been established to fill the need for consortium-based testing of e-beam resists for mask writing applications on advanced mask writers out to the 11nm half-pitch node and beyond. SEMATECH and the College of Nanoscale Science and Engineering (CNSE) began establishing the ERTF in early 2012 to test e-beam resist samples from commercial suppliers and university labs against the required performance metrics for each application at the target node. Operations officially began on June 12, 2012, at which time the first e-beam resist samples were tested. The ERTF uses the process and metrology infrastructure available at CNSE, including a Vistec VB300 Vectorscan e-beam tool adjusted to operate at 50kv. Initial testing results show that multiple resists already meet, or are close to meeting, the resolution requirements for mask writing at the 11nm node, but other metrics such as line width roughness still need improvement.
An overview of the ERTF and its capabilities is provided here. Tools, baseline processes, and operation strategy details are discussed, and resist testing and benchmarking results are shown. The long-term outlook for the ERTF and plans to expand capability and testing capacity, including resist testing for e-beam direct write lithography, are also discussed.
A survey supported by SEMATECH and administered by David Powell Consulting was sent to semiconductor industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. 2012 marks the 11th consecutive year for the mask industry survey. This year’s survey and reporting structure are similar to those of the previous years with minor modifications based on feedback from past years and the need to collect additional data on key topics. Categories include general mask information, mask processing, data and write time, yield and yield loss, delivery times, and maintenance and returns. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the mask industry. Results, initial observations, and key comparisons between the 2011 and 2012 survey responses are shown here, including multiple indications of a shift towards the manufacturing of higher end photomasks.
The semiconductor and hard disk drive industries are investigating nanoimprint for future high volume manufacturing of memory devices and patterned media. Nanoimprint, a form of 1× contact lithography, is one of the few technologies capable of meeting the resolution requirements for next generation electronic and storage devices. Its ability to produce small features with low line width roughness and critical dimension uniformity has been demonstrated by multiple sources. Significant improvements in defectivity have been shown; overlay has improved to within a factor of 2 of that required by the International Technology Roadmap for Semiconductors for 22 nm node flash memory devices; and next generation tools, templates, and processes are being commercialized and tested at end-user sites. Defectivity, throughput, and infrastructure remain as critical challenges, but each has experienced marked improvements in the past year. This technology review and assessment covers critical aspects of nanoimprint for both semiconductor and patterned media manufacturing. It focuses on jet and flash imprint lithography, the type of nanoimprint most often considered for these two applications. The requirements and current status of nanoimprint with respect to high volume manufacturing are presented, and critical aspects are discussed.
Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint
lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet
defect requirements originates in part from the industry's past experiences with 1X lithography and the shortage in end-user
generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns.
The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints,
is capable of meeting semiconductor industry defect requirements.
At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results.
J-FIL process random defectivity of < 0.1 def/cm2 has been demonstrated using a 120nm half-pitch template, providing
proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly
as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm.
Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for
its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the
resolution requirements of future semiconductor devices. However, many integration issues such as defectivity,
throughput, and overlay must be resolved before SFIL can be used for semiconductor high volume manufacturing
(HVM). This paper discusses the current status of SFIL, including the process and templates, and shows where more
industry collaboration is needed to solve the most critical issues.
SEMATECH has initiated a nanoimprint program and started imaging experiments with a Molecular Imprints
Imprio300TM system at the SEMATECH facility in Albany, NY. An overview of the SEMATECH nanoimprint
development program is presented as well as an assessment of nanoimprint technology strengths and weaknesses.
SEMATECH plans to explore many of the critical aspects of the nanoimprint process to drive key improvements in
overlay, imprint mask cleaning, and defectivity toward making nanoimprint technology a cost-effective lithography
strategy for CMOS development and manufacturing applications. Results of nanoimprint overlay with a previous level
exposed on a 1.35NA immersion lithography scanner show it has noticeably improved over previous results with
champion data in the 18nm range. Imprint mask cleaning on an automated tool has shown no measurable degradation of
critical dimension or line width roughness after ten cleaning cycles.
This paper describes our initial investigation into building a greater understanding of the complex mechanism occurring during extreme ultraviolet (EUV) exposure of resist materials. In particular, we are focusing on the number and energy of photoelectrons generated and available for reaction with photoacid generators (PAGs). We propose that this approach will best enable the industry to develop resists capable of meeting resolution, line width roughness (LWR), and sensitivity requirements.
Base titration methods are used to determine C-parameters for three industrial EUV photoresist platforms (EUV-
2D, MET-2D, XP5496) and twenty academic EUV photoresist platforms. X-ray reflectometry is used to measure the
density of these resists, and leads to the determination of absorbance and film quantum yields (FQY). Ultrahigh levels
of PAG show divergent mechanisms for production of photoacids beyond PAG concentrations of 0.35 moles/liter. The
FQY of sulfonium PAGs level off, whereas resists prepared with iodonium PAG show FQYs that increase beyond PAG
concentrations of 0.35 moles/liter, reaching record highs of 8-13 acids generated/EUV photons absorbed.
The availability of photoresists meeting simultaneous resolution, sensitivity, and line edge roughness performance is a critical challenge for the acceptance of Extreme Ultraviolet Lithography. The Extreme Ultraviolet Resist Test Center (EUV RTC) at SEMATECH-North at the State University of New York at Albany is a state of the art facility to support the development of photoresists for EUV lithography. The facility was opened on September 28, 2005, for customer use. SEMATECH researchers, member companies, resist suppliers, and researchers from universities and institutes worldwide can use this neutral site for EUV resist development. The heart of the EUV RTC is an Exitech 5X EUV microstepper with a 0.3 numerical aperture (NA) lens. This tool has successfully imaged 45 nm dense lines in photoresists, and the ultimate imaging performance of the microstepper based on optics and wavefront quality should be near 25nm dense lines.
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