Organic flexible electronics is an emerging technology with huge potential growth in the future which is likely to open
up a complete new series of potential applications such as flexible OLED-based displays, urban commercial signage, and
flexible electronic paper. The transistor is the fundamental building block of all these applications. A key challenge in
patterning transistors on flexible plastic substrates stems from the in-plane nonlinear deformations as a consequence of
foil expansion/shrinkage, moisture uptake, baking etc. during various processing steps.
Optical maskless lithography is one of the potential candidates for compensating for these foil distortions by in-situ
adjustment prior to exposure of the new layer image with respect to the already patterned layers. Maskless lithography
also brings the added value of reducing the cost-of-ownership related to traditional mask-based tools by eliminating the
need for expensive masks. For the purpose of this paper, single-layer maskless exposures at 355 nm were performed on
gold-coated poly(ethylenenaphthalate) (PEN) flexible substrates temporarily attached to rigid carriers to ensure
dimensional stability during processing. Two positive photoresists were employed for this study and the results on plastic
foils were benchmarked against maskless as well as mask-based (ASML PAS 5500/100D stepper) exposures on silicon
wafers.
The exponential increase in areal density of magnetic hard disk drives during the last years has led to incredibly tighter manufacturing tolerances. For the lithography process that is being used to make the principal component in a hard disk drive, the read-write head, this means that improved process control is required with respect to imaging and positioning performance. Beside the overlay performance from layer to layer, the relative placement of images in a single critical layer is being looked at as an important performance requirement on state-of-the-art DUV and I-line steppers. The terms stitching and co-linearity characterize the relative placement of images in a single layer. In this paper verification tests for stitching and co-linearity are presented, as they are developed by ASML. Since these tests require an understanding of the terms stitching and co-linearity, the definitions of these terms are outlined. The results for the two tests on an ASML PAS 5500/300 DUV stepper are presented and discussed. Also the effects of certain error sources and some ideas for future optimization are shown.
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