A cost-efficient technique for full-chip source and mask optimization is proposed in this paper. This technique has two
components: SMO source optimization for full-chip and flexible mask optimization (FMO). During the technology
development stage of source optimization, a novel pattern-selection technique was used to identify critical clips from a
full-set of design clips; SMO was then used to optimize the source based on those selected critical-clips. This pattern-selection
technique enables reasonable SMO runtime to optimize the source that covers the full range of patterns. During
the process development stage and product tapeout stage, FMO is employed. The FMO framework allows the use of
different OPC computational techniques on different chip areas that have different sensitivities to process variations.
Advanced OPC methods are applied only where they are needed, therefore achieving optimum process performance with
the least tapeout and mask cost.
A fast model-based technique for SRAF placements is proposed in this paper. This technique first constructed an image
pixel map with values presenting the sensitivity of improving process window on the desired pattern. The sensitivity
value was derived based on contrast improvement with a defocus model. Then high value pixels were selected and
constructed to form SRAF with MRC regulations. This technique does not require iterations to produce SRAF and
achieves very fast runtime with simple mask shapes, thus can be used in full-chip productions. We called this technique
the SRAF guidance map, SGM
The use of customized illumination modes is part of the pursuit to stretch the applicability of immersion ArF lithography.
Indeed, a specific illumination source shape that is optimized for a particular design leads to enhanced imaging results.
Recently, freeform illumination has become available through pixelated DOEs or through FlexRayTM, ASML's
programmable illuminator system, allowing for virtually unconstrained intensity distribution within the source pupil.
In this paper, the benefit of freeform over traditional illumination is evaluated, by applying source mask co-optimization
(SMO) for an aggressive use case, and wafer-based verification. For a 22 nm node SRAM of 0.099 μm² and 0.078 μm2
bit cell area, the patterning of the full contact and metal layer into a hard mask is demonstrated with the application of
SMO and freeform illumination. In this work, both pixelated DOEs and FlexRay are applied. Additionally, the match
between the latter two is confirmed on wafer, in terms of CD and process window.
We proposed a new method of generating and optimizing sub-resolution assist features (SRAFs). This method is based
on a newly proposed ILT algorithm-Cost-function-Reduction method (CFRM). CFRM is proved to be much effective
and efficient than gradient-based algorithm and traditional simulated annealing method. We improve CFRM to be an
initial condition independent algorithm (ICIA) by tuning some running parameters. The robustness of ICIA is verified
numerically by six mask patterns and two mask technologies in partial-coherence image model using 100 randomly
generated mask patterns. Results showed that all are converged to similar final mask patterns with less than 3%
differences of the final image edge placement error (EPE). The skeleton of the final mask pattern can be decided by first
tens of iterations. Based on the above properties, an efficient and effective algorithm is proposed to handle SRAFs
placement. This effectiveness method is demonstrated by different patterns using different mask technologies.
A novel high-resolution model (HRM) filtering technique was proposed to describe litho-constrained layouts. Litho-constrained
layouts are layouts that have difficulties to pattern or are highly sensitive to process-fluctuations under
current lithography technologies. HRM applies a short-wavelength (or high NA) model simulation directly on the pre-OPC, original design layout to filter out low spatial-frequency regions, and retain high spatial-frequency components
which are litho-constrained. Since no OPC neither mask-synthesis steps are involved, this new technique is highly
efficient in run time and can be used in design stage to detect and fix litho-constrained patterns. This method has
successfully captured all the hot-spots with less than 15% overshoots on a realistic 80 mm2 full-chip M1 layout in 65nm
technology node. A step by step derivation of this HRM technique is presented in this paper.
A significant barrier to implementing APSM in volume production has been the expense of the mask. The cost of the
mask is driven partially by the complexity of the two layer process flow required to make the mask. Typically, the 2nd
level pattern is generated by upsizing the first level pattern of the pi apertures by a small amount in order to provide
some overlay margin. The amount of upsizing is limited by the smallest chrome feature present in the pattern. The
overlay margin between the first and 2nd level patterns can be improved by sizing the 2nd level more on larger chrome
structures, when present. With a simple set of rules, it is possible to generate a 2nd level pattern with greater than ten
times reduction in the number of corners, as measured by the number of vertices in the pattern, and minimize the number
of marginal patterns in the design. This also has the beneficial side effect of significantly reducing the file size of the 2nd
level pattern which can reduce the write time on some writers. Existing design rules can be exploited or additional rules
imposed that can further improve the capability of the 2nd level APSM process. The right set of mask design rules can
enable the use of lower fidelity writer for 2nd level patterning which can significantly reduce cost. The improved margin
can increase yield and may even enable a less capable/expensive patterning tool to be used for 2nd level patterning.
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