Every couple of decades a major semiconductor crisis arises even though some clues on the origin of the crisis could have been predicted in advance and possible solutions could have been identified in advance. The International Roadmap for Semiconductors (ITRS) was created to provide needed leadership and its evolution to the International Roadmap for Devices and Systems (IRDS) continues to play a key role in guiding implementation of the most viable solutions. Four semiconductor crises that occurred over the past 60 years are notable. The development and evolution of the semiconductor roadmap and its vital role in guiding the industry is presented.
The semiconductor industry has been and remains the engine of the electronics revolution that has completely change society for the better. 2D transistor performance and transistor count have steadily increased for the past 70 years. 2D “geometrical scaling” was the engine of the semiconductor industry until the end of the previous century. By that time some fundamental physical limits were reached and overcome by completely restructuring the transistor and replacing some of the original materials. This second era was named “equivalent scaling”. In this decade, memory technologies have already reached the cost effective limits of 2D scaling and have migrated to “3D power scaling”. Logic will transition to 3D structures and architectures in the near future. However, 3D power scaling will also reach practical topological limits in the next 15 years and it will be then necessary to implement computing techniques that operate with more than one bit in any physical location to support the 4th age of Moore’s Law. What can the electronics industry do to get ready for it?
“Geometrical Scaling” of MOS transistors supported the growth of the electronics industry for over 25 years (1975~2000) in accordance with Moore’s Law. The NTRS identified in the mid-90s major upcoming material and structural limitations of the silicon-gate transistor. To solve these problems the ITRS was formed in 1998 and the concepts of strained silicon, high-κ/metal gate, FinFET, and introduction of other semiconductor materials under “Equivalent Scaling” were identified as possible solutions to overcome these limitations. By 2011 all these new innovative technologies had been introduced into manufacturing. This approach has giving the semiconductor industry another 25 years (2000~2025) of growth. Realization of continuously smaller horizontal (2D) features will reach fundamental limits by ~2025. Flash producers have already transformed the realization of transistors from the horizontal dimension to the vertical dimension to solve this problem. Logic producers will follow. IRDS assessed that “3D Power Scaling” will extend Moore’s Law for at least another 15 years (2025~2040). How would implementation of 3D transistor and circuit affect lithographic requirements?
The semiconductor industry benefitted from roadmap guidance since the mid-60s. The roadmap
anticipated and outlined the main needs of the semiconductor industry for years to come and identified
future challenges and possible solutions. Making transistor smaller by means of advanced lithographic
technologies enabled both increased integration levels and improved IC performance. The roadmap
methodology allowed the removal of multiple “red brick walls”. The NTRS and the ITRS constituted
primarily a “bottom up” approach as standard microprocessors and memories where introduced at a
blistering pace barely allowing time for system houses to integrate them in their products. The 1998
ITRS provided the vision that triggered research, development and manufacturing communities to
develop a completely new transistor structure in addition to replacing aluminum interconnects with a
more advanced technology. The advent of Foundries and Fabless companies transformed the electronics
industry into a “top down” driven industry in the past 15 years. The ITRS adjusted to this new
ecosystem and morphed into the International Roadmap for Devices and Systems (IRDS) sponsored by
IEEE. The IRDS is addressing the requirements and needs of the renewed electronics industry.
Furthermore, by the middle of the next decade the ability to layout integrated circuits in a 2D geometry
grid will reach fundamental physical limits and the aggressive conversion to 3D architecture for
integrated circuit must be pursued across the board as an avenue to continuously increasing transistor
count and improving performance. EUV technology is finally approaching the manufacturing stage but
with the advent of 3D monolithically integrated heterogeneous circuits approaching in the not-toodistant
future should the semiconductor industry concentrate its resources on the next lithographic
technology generation in order to enhance resolution or on providing a smooth transition to the new
revolutionary 3D architecture of integrated circuits? It is essential for the whole semiconductor industry
to come together and make fundamental choices leading to a cooperative and synchronized allocation of
adequate resources to produce viable solutions that once introduced in a timely manner into
manufacturing will enable the continuation of the growth of the electronic industry at a pace
comparable or exceeding historical trends.
The semiconductor industry has successfully undergone two major transitions in the 70's and in the 80's, that have been followed by long periods of sustained growth. A third transition is approaching in the second half of this decade that promises to fuel the growth of the semiconductor industry well into the second decade of this century, if well executed. Many new materials and a renewed MOS structure will be necessary to revitalize the basic device capabilities. Lithography technology is a key enabler of the semiconductor industry. After a decade of discussions and heated debates, the lithography roadmap has been finally internationally accepted and the wavelengths of choice identified and agreed upon: 193nm, 157nm, and 13.5nm. Execution is now the name of the game. As the level of investments required for the development and deployment of the overall lithography infrastructure continues to escalate with time and as execution on a tight time table is a must, it is necessary to resort to any available cooperation among consortia, supplier companies and IC companies to maintain the semiconductor industry on the historical 25-30 percent cost reduction per function per year that has been, and still remains, at the center of its success.
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