Dr. Rafal Dlugosz Profile

Dr. Rafal Dlugosz

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Publications (6)

Proceedings Article | 10 May 2007 Paper

Flexible and low power binary-tree current mode min/max nonlinear filters realized in CMOS technology

R. Długosz, T. Talaśka

Proceedings Volume 6590, 65900L (2007) https://doi.org/10.1117/12.721192

KEYWORDS: Nonlinear filtering, Image processing, Filtering (signal processing), Signal processing, Clocks, Photomasks, Switches, CMOS technology, Electronic filtering, Chemical elements

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Proceedings Article | 10 May 2007 Paper

Ultra low power switched current finite impulse response filter banks realized in CMOS 0.18 um technology

Rafał Długosz

Proceedings Volume 6590, 65900H (2007) https://doi.org/10.1117/12.721162

KEYWORDS: Optical filters, Finite impulse response filters, Transistors, Electronic filtering, Sensor networks, Mirrors, Clocks, Filtering (signal processing), Switches, Discrete wavelet transforms

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Proceedings Article | 10 May 2007 Paper

Synchronous and asynchronous multiplexer circuits for medical imaging realized in CMOS 0.18um technology

R. Długosz, K. Iniewski

Proceedings Volume 6590, 65900V (2007) https://doi.org/10.1117/12.721239

KEYWORDS: Clocks, Multiplexers, Signal detection, Sensors, Multiplexing, Analog electronics, Transistors, Medical imaging, Switches, CMOS technology

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Multiplexers are one of the most important elements in readout front-end ASICs for multi-element detectors in medical imaging. The purpose of these ASICs is to detect signals appearing randomly in many channels and to collect the detected data in an ordered fashion (de-randomization) in order to send it to an external ADC. ASIC output stage functionality can be divided into two: pulse detection and multiplexing. The pulse detection block is responsible for detecting maximum values of signals arriving from the shaper, sending a flag signal indicating that the peak signal has been detected and storing the pulse in an analog memory until read by ADC. The multiplexer in turn is responsible for searching for active flags, controlling the channel that has detected the peak signal and performing reset functions after readout. There are several types of multiplexers proposed in this paper, which can be divided into several classes: synchronous, synchronized and asynchronous. Synchronous circuits require availability of the multiphase clock generator, which increases the power dissipation, but simultaneously provide very convenient mechanism that enables unambiguous choice of the active channel. This characteristics leads to 100% effectiveness in data processing and no data loss. Asynchronous multiplexers do not require clock generators and because of that have simpler structure, are faster and more power efficient, especially when data samples occur seldom at the ASIC's inputs. The main problem of the asynchronous solution is when data on two or more inputs occur almost at the same time, shorter than the multiplexer's reaction time. In this situation some data can be lost. In many applications loss of the order of 1% of the data is acceptable, which makes use of asynchronous multiplexers possible. For applications when the lower loss is desirable a new hierarchy mechanism has been introduced. One of proposed solutions is a synchronized binary tree structure, that uses many simple asynchronous clock generators. This circuit joins advantages of synchronous and asynchronous solutions resulting in low power dissipation, high speed of operation and 100% effectiveness.

Proceedings Article | 30 June 2005 Paper

Search strategy for relevant parasitic elements and reduction of their influence on the operation of SC FIR filters realized in CMOS technology

Rafal Dlugosz

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608632

KEYWORDS: Finite impulse response filters, Optical filters, Computer aided design, CMOS technology, Integrated circuits, Clocks, Capacitors, Digital filtering, Signal attenuation, Analog electronics

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Parasitic capacities pose a serious problem in switched capacitor finite impulse response (SC FIR) filters realized as VLSI systems in CMOS submicron technologies. The influence of these parasitic elements is especially visible in the stopband of the filter frequency response. To design mixed digital-analog SC FIR filters is a difficult task. Filters of this class have to be designed using full-custom method. SC FIR filters of high orders N are very complex systems with thousands of transistors, capacitors, which, in turn, make the basis for many active elements, switches, delay elements, memories and other circuitry. One of the most important stages during the design process is post-layout HSPICE verification. However, the simulation of separated blocks does not suffice to have enough knowledge of the operation of the whole system. Optimization requires netlist simulations of the entire system, with presence of typically between 5000-30000 of parasitic capacities, where only about hundred of them are critical ones. Analysis which aims at finding these elements, in practice, is not possible because of the complexity of the entire system. The heuristic method of searching for relevant parasitic elements presented in this paper is based on the assumption that all parasitic elements create a set. The main task is to divide this set into subareas. In order to do this particular groups of nets in the layout must be labeled using unique names. Then particular groups of parasitic elements are filtered out from the netlist. Each filtering stage generates two netlists with separate areas of parasitic elements. After the analysis of the simulation results has been done there remains to make the decision concerning subsequent filtering operations. The iteration method is very quick, convenient, efficient and does not require deep knowledge of the simulated system. Many stages of this method can be easy implemented with CAD tools. In realized projects, after no more than 15-60 iterations critical parasitic capacities were found. In realization of the four chips in CMOS 0.8mm and 0.35mm technologies this method issued in very good results-the attenuation in the stopband, which is very important parameter, was improved by about 20-25 dB.

Proceedings Article | 30 June 2005 Paper

Voltage-buffer-based low-power area-efficient SC FIR filter for wireless communication

Rafal Dlugosz, Ryszard Wojtyna

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608241

KEYWORDS: Optical filters, Digital filtering, Capacitors, Finite impulse response filters, Clocks, Amplifiers, Signal processing, Transistors, CMOS technology, Chemical elements

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Proceedings Article | 30 June 2005 Paper

Multiphase clock generators with controlled clock impulse width for programmable high order rotator SC FIR filters realized in 0.35 µm CMOS technology

Rafal Dlugosz, Pawel Pawlowski, Adam Dabrowski

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608490

KEYWORDS: Clocks, Finite impulse response filters, Transistors, CMOS technology, Optical filters, Control systems, Capacitors, Signal attenuation, Electronic filtering, Signal processing

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Showing 5 of 6 publications

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