Measuring EPE on logic devices is challenging due to the large variety of features given its random environment and layout. One has to measure an enormous amount of unique features to estimate CD, PPE, LCDU, and LPE of each feature making it impractical for EPE monitoring due to the large metrology load. We developed a simulation-based pattern clustering method that identifies and classifies features with similar EPE behavior to address this challenge. Both geometric design and imaging behavior of the patterns were taken into account to effectively cluster similar features. We report here the verification results of the clustering method which is measured on-wafer for both random layout lines-spaces and vias. With this we make a step towards identification and selection of EPE critical patterns for logic devices, which can be used further for monitoring and control.
The grouping method assisted EPE-aware control method is being explored in a multi-feature dual layer Logic use case. EPE metric is estimated using angle resolved optical Scatterometry based overlay and electron beam-based metrology (large field of view SEM) for the reconstruction of edge-to-edge distance between the Metal and Via pattern. In the setup phase, EPE sensitivities to dose and focus have been derived using data from a FEM wafer. EPE-aware optimization, using scanner dose and overlay control sub-recipes, outperforms traditional optimization in simulations showing reduced EPE max per die. This improvement suggests a potential increase in device yield through the adoption of EPE-aware control strategies. To verify this performance improvement on wafers, an experiment is needed with minimal wafer to wafer and lot to lot variations which can be achieved by reducing time between lots and increasing the number of wafers measured.
As the term EPE was coined in the 1990ties, more recently a more inclusive definition of EPE has been proposed. Meanwhile semiconductor manufacturers see EPE as one of the main performance metrics enabling further shrink.
In this paper we will give an update on the latest developments on EPE. Considering logic and memory use cases we will present evaluations of the EPE budget, including OPC model accuracy, overlay, CDU fingerprints for intra-field and inter field, overlay and local CD and placement error.
The EPE fingerprint characterization is used to optimize scanner control for EPE performance on product. We will show how we can optimize the measured EPE fingerprints using scanner actuators.
We demonstrate the use of EPE (Edge Placement Error) as an early defect detection metric in an EUV self-aligned lithoetch-litho-etch (eSALELE) patterning process. Pitch 21nm test structures were investigated on an eSALELE flow consisting of 4 EUV exposures, 2 of which are lines-spaces while the other 2 exposures are for block patterns that defines the tip-to-tip. An HMI eP5 SEM with large field-of-view (8x8µm FOV) was used to measure critical dimension (CD) on wafer at each critical processing step while the overlay between multiple exposures were measured optically on uDBO marks using a YieldStar (YS). On top of CD metrology, patterning defects were measured at the final patterning transfer into dielectric material using an eP5 SEM and built-in defect inspection capability. Line-break defects are reported. Although each metric like CD, LWR or OVL is expected to contribute to the defect performance of the final pattern transfer, using only one information or another is not fully descriptive. Combining these information into an EPE metric on this complicated patterning process showed better correlation to the defect rates at dielectric transfer.
We present an experimental study of pattern variability and defectivity, based on a large data set with more than 112 million SEM measurements from an HMI high-throughput e-beam tool. The test case is a 10nm node SRAM via array patterned with a DUV immersion LELE process, where we see a variation in mean size and litho sensitivities between different unique via patterns that leads to a seemingly qualitative differences in defectivity. The large available data volume enables further analysis to reliably distinguish global and local CDU variations, including a breakdown into local systematics and stochastics. A closer inspection of the tail end of the distributions and estimation of defect probabilities concludes that there is a common defect mechanism and defect threshold despite the observed differences of specific pattern characteristics. We expect that the analysis methodology can be applied for defect probability modeling as well as general process qualification in the future.
In the advent of multiple patterning techniques in semiconductor industry, metrology has progressively become a burden. With multiple patterning techniques such as Litho-Etch-Litho-Etch and Sidewall Assisted Double Patterning, the number of processing step have increased significantly and therefore, so as the amount of metrology steps needed for both control and yield monitoring. The amount of metrology needed is increasing in each and every node as more layers needed multiple patterning steps, and more patterning steps per layer. In addition to this, there is that need for guided defect inspection, which in itself requires substantially denser focus, overlay, and CD metrology as before. Metrology efficiency will therefore be cruicial to the next semiconductor nodes. ASML's emulated wafer concept offers a highly efficient method for hybrid metrology for focus, CD, and overlay. In this concept metrology is combined with scanner's sensor data in order to predict the on-product performance. The principle underlying the method is to isolate and estimate individual root-causes which are then combined to compute the on-product performance. The goal is to use all the information available to avoid ever increasing amounts of metrology.
As leading edge lithography moves to advanced nodes, CDU requirements have relatively increased with technologies 14nm/20nm and beyond. In this paper, we want to introduce the methodology to offer an itemized CDU budget such as Intra-field, Inter-field, wafer to wafer as well as scanner contributors vs. non-scanner contributors (including detailed analysis of reticle contributors like CD, absorber thickness and SWA variation) through Top-Down CDU and Bottom-Up CDU budget breakdown and deliver sources of CD variation with measureable value so that we can estimate CDU gain from them. The test vehicle being used in this experiment is designed based on 14nm D/R basis. Measurement structures are densely located in the slit/scan direction on the reticle for the data collection plan. Hence, we can expand on this methodology to build up the tool reference fingerprint when we release new tool fleet. The final goal will be to establish a methodology for CDU budget breakdown that can be used to draw a conclusion on the root causes of the observed CDU, propose its improvement strategy and estimate the gain.
KEYWORDS: Semiconducting wafers, Data modeling, Metrology, Defect detection, High volume manufacturing, Deep ultraviolet, Inspection, Detection and tracking algorithms, Process control, Etching, Optical lithography, Scanning electron microscopy, Sensors, Lithography, Scanners
As process window margins for cutting edge DUV lithography continue to shrink, the impact of systematic patterning defects on final yield increases. Finding process window limiting hot spot patterns and monitoring them in high volume manufacturing (HVM) is increasingly challenging with conventional methods, as the size of critical defects can be below the resolution of traditional HVM inspection tools. We utilize a previously presented computational method of finding hot spot patterns by full chip simulation and use this to guide high resolution review tools by predicting the state of the hot spots on all fields of production wafers. In experiments with a 10nm node Metal LELELE vehicle we show a 60% capture rate of after-etch defects down to 3nm in size, at specific hot spot locations. By using the lithographic focus and dose correction knobs we can reduce the number of patterning defects for this test case by ~60%.
In this paper we describe the joint development and optimization of the critical dimension uniformity (CDU) at an advanced 300 mm ArFi semiconductor facility of SK Hynix in the high volume device. As the ITRS CDU specification shrinks, semiconductor companies still need to maintain high wafer yield and high performance (hence market value) even during the introduction phase of a new product. This cannot be achieved without continuous improvement of the on-product CDU as one of the main drivers for yield improvement. ASML Imaging Optimizer is one of the most efficient tools to reach this goal. This paper presents experimental results of post-etch CDU improvement by ASML imaging optimizer for immature photolithography and etch processes on critical features of 20nm node. We will show that CDU improvement potential and measured CDU strongly depend on CD fingerprint stability through wafers, lots and time. However, significant CDU optimization can still be achieved, even for variable CD fingerprints. In this paper we will review point-to-point correlation of CD fingerprints as one of the main indicators for CDU improvement potential. We will demonstrate the value of this indicator by comparing CD correlation between wafers used for Imaging Optimizer dose recipe development, predicted and measured CDU for wafers and lots exposed with various delays ranging from a few days to a month. This approach to CDU optimization helps to achieve higher yield earlier in the new product introduction cycle, enables faster technology ramps and thereby improves product time to market.
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