Recently, both PSI1 and ASML2 illustrated champion EUVL resolution using slow, non-chemically amplified inorganic resists. However, the requirements for EUVL manufacturing require simultaneous delivery of high resolution, good
sensitivity, and low line edge/width roughness (LER/LWR) on commercial grade hardware. As a result, we believe that
new classes of materials should be explored and understood. This paper focuses on our efforts to assess metal oxide based
nanoparticles as novel EUV resists3. Various spectroscopic techniques were used to probe the patterning
mechanism of these materials. EUV exposure data is presented to investigate the feasibility of employing inorganic
materials as viable EUV resists.
The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a
leading technology option for realizing the 22nm half pitch node and beyond. According to recent assessments made at
the 2010 EUVL Symposium, the readiness of EUV materials remains one of the top risk items for EUV adoption. The
main development issue regarding EUV resists has been how to simultaneously achieve high resolution, high sensitivity,
and low line width roughness (LWR). This paper describes our strategy, the current status of EUV materials, and the
integrated post-development LWR reduction efforts made at Intel Corporation. Data collected utilizing Intel's Micro-
Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously
exhibits ≤22nm half-pitch (HP) L/S resolution at ≤11.3mJ/cm2 with ≤3nm LWR.
Since its installment in 2004, Intel's extreme ultraviolet (EUV) micro-exposure tool (MET) has demonstrated significant
improvements in ultimate resolution capability. Initially capable of printing 45nm half-pitch (HP) lines with a 160nm
depth of focus (DOF), it is now capable of printing 22nm HP lines with up to a 275nm DOF and demonstrating
modulation down to 18nm HP. Initial improvements in resolution have been chiefly attributable to the maturation of
EUV masks and photoresists. Recent improvements that have enabled the 22nm HP imaging with a sizeable process
window are largely due to new illumination options that have become available as a result of recent tool upgrades. In
particular, the installation of a new nested Wolter collector with an additional outer shell that extended the maximum
partial coherence (σ) from 0.55 to 0.68, in conjunction with an updated pupil wheel and apertures, has enabled new
rotated quadrapole and on-axis dipole illumination settings with 0.36 inner σ and 0.68 outer σ. Here we present simulated
contrast curves alongside the experimental imaging results for the Intel MET using the newly available quadrapole and
on-axis dipole illumination settings and discuss our future plans for continued improvements to the Intel MET aerial image.
Assessing the printability of EUV (extreme ultraviolet) lithography mask pattern defects is critical for determining EUV
mask patterning, defect metrology, and repair technology requirements. Printability of mask defects at the wafer level
depends on defect size, defect shape, defect location, and the line width and pitch of the structure being printed. Earlier
reports showed the relationship between the defect size on the mask and the printed critical dimension for 40-70 nm
dense lines. Improvements in the EUVL process now enable assessment of mask pattern defect printability for 22-40
nm half-pitch features.
We report here the smallest mask pattern defects that printed at different locations in 22-40 nm structures using the Intel
Micro-Exposure Tool (MET). Various types of defects such as indentations or protrusions were purposely incorporated
into features on an EUV mask. The sizes of the patterned defects on the mask were drawn between 10-250 nm (= 2-50
nm on the wafer). The minimum printable defect size varied by over 100 nm, depending on the defect shape and
location.
Reducing mask blank and patterned mask defects is the number one challenge for extreme ultraviolet lithography. If the
industry succeeds in reducing mask blank defects at the required rate of 10X every year for the next 2-3 years to meet
high volume manufacturing defect requirements, new inspection and review tool capabilities will soon be needed to
support this goal. This paper outlines the defect inspection and review tool technical requirements and suggests
development plans to achieve pilot line readiness in 2011/12 and high volume manufacturing readiness in 2013. The
technical specifications, tooling scenarios, and development plans were produced by a SEMATECH-led technical
working group with broad industry participation from material suppliers, tool suppliers, mask houses, integrated device
manufacturers, and consortia. The paper summarizes this technical working group's assessment of existing blank and
mask inspection/review infrastructure capabilities to support pilot line introduction and outlines infrastructure
development requirements and tooling strategies to support high volume manufacturing.
The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a
leading technology option for realizing the 22nm half pitch node and beyond. Readiness of EUV materials is currently
one high risk area according to recent assessments made at the 2009 EUVL Symposium. The main development issue
regarding EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width
roughness (LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation.
Data collected utilizing Intel's Micro-Exposure Tool (MET) is presented in order to examine the feasibility of
establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤ 12.5mJ/cm2 with
≤ 4nm LWR.
EUV lithography (EUVL) is a leading candidate for printing sub-32 nm hp patterns. In order for EUVL to be
commercially viable at these dimensions, a continuous evolution of the photoresist material set is required to
simultaneously meet the aggressive specifications for resolution, resist sensitivity, LWR, and outgassing rate.
Alternative PAG designs, especially if tailored for EUVL, may aid in the formation of a material set that helps
achieve these aggressive targets. We describe the preparation, characterization, and lithographic evaluation of
aryl sulfonates as non-ionic or neutral photoacid generators (PAGs) for EUVL. Full lithographic
characterization is reported for our first generation resist formulation using compound H, MAP-1H-2.5. It is
benchmarked against MAP-1P-5.0, which contains the well-known sulfonium PAG, triphenylsulfonium
triflate (compound P). Z-factor analysis indicates nZ32 = 81.4 and 16.8 respectively, indicating that our first
generation aryl sulfonate formulations require about 4.8x improvement to match the results achieved with a
model onium PAG. Improving the acid generation efficiency and use of the generated byproducts is key to
the continued optimization of this class of PAGs. To that end, we believe EI-MS fragmentation patterns and
molecular simulations can be used to understand and optimize the nature and efficiency of electron-induced
PAG fragmentation.
The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a
leading technology option for realizing the 32nm half-pitch node and beyond. Readiness of EUV materials is currently
one high risk area according to assessments made at the 2008 EUVL Symposium. The main development issue regarding
EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width roughness
(LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation. Data is
presented utilizing Intel's Micro-Exposure Tool (MET) examining the feasibility of establishing a resist process that
simultaneously exhibits ≤30nm half-pitch (HP) L/S resolution at ≤10mJ/cm2 with ≤4nm LWR.
EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices
[1]. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule
restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and
lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to
demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper
yield. A patterning demonstration of Intel's 32 nm test chips using the ADT at IMEC [7] is presented, This test chip
was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intel's mask
shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT
which resulted in a large k1 factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It
was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these
originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist,
overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.
Nonionic photoacid generators (PAGs) based on photosensitive fluoroorganic sulfonate esters of imide and nitrobenzyl have been prepared and characterized. These new compounds produce fluoroorganic sulfonic acids that contain very few fluorine atoms (non-PFOS), which make them attractive PAGs for all advanced and emerging lithography. The structural influence of these new PAGs on sensitivity, resolution and line edge roughness (LER) was investigated by using DUV (254 nm) and e-beam lithography with ESCAP and ACRYLIC type positive tone resists. E-beam lithography evaluation indicates that these new fluroorganic sulfonic acids are sensitive and capable of providing image profiles down to 80 nm. The variation observed in sensitivity and LER at e-beam lithography was analyzed in terms of the structures of the photogenerated acids, chromophores and resists.
Intel’s recent 157nm fluoropolymer photoresist development is described, including the benchmarking of photoresist patterning and the suitability of resists in typical Intel etch processes. The imaging results show that the new ultra-low absorbance resists (absorbance <1/μm) show great promise for meeting the 65nm-node ITRS targets. The materials also show good etch resistance when exposed to SiO2, Si3N4 and SixOyNz dry etch chemistries.
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