The goal of this study is to discuss the findings of experiments we conducted to enhance defect capture rate in the advanced nodes design-for-manufacturing flow. As a metric of manufacturing excellence, wafer fabrication units track and report defect density on a regular basis. Fabrication with a reduced defect density can produce a higher chip yield. In recent years, systematic defects resulting from design and process have been predicted to be the leading cause of yield loss. This could result in a large rise in manufacturing costs and time. As a result, they are highly undesirable, and it is critical to accurately identify them for root analysis of weak patterns. Unlike random process defects, systematic patterning defects may show characteristic design features and our goal is to leverage these to create a machine learning model that can efficiently identify and categorize these defects before they get into production. An inherent problem that we face is class imbalance: high confidence defect data constitutes a few thousand samples for maturing nodes and nondefects of the order of millions. Additionally, millions of records in the train, test, and inference datasets, even with reduced feature sets, can lead to a host of big data issues like insufficient memory, large experiment times, and lack of integrated development. In this paper, we discuss methodologies to handle the large volume, imbalanced data which led to 47% improvement in the defect capture and 100% improvement in the noise to signal ratio.
Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle, in turn saving time and efforts. In this paper, we describe a new bottom-up approach to layout risk assessment that can rapidly identify unique patterns in layouts, and in combination with techniques like feature filters, location mapping and clustering, can pre-determine their criticality. A massive highly performant pattern database of single and multilayer patterns, along with their features and locations, forms the core of the system. While pattern analyses may be pertaining to the short range of design space, silicon defects and simulations extend to a much larger scope. Therefore, the database is extended to defect data extracted from Silicon inspection tools like Bright Field Inspection (BFI) and Scanning Electron Microscopy (SEM). When stored in an optimized manner, it can aid fast and efficient large data analysis and machine learning within critical tapeout review time which is typically a few days. Machine learning combined with design feature filters can then be used for anomaly detection and failure prediction at layout, layer and pattern levels. As a result, outlier patterns can be visually reviewed and flagged for custom targeted simulations and silicon inspection. Further, adding new layout patterns to the pattern database will make it possible to repeat this exercise for subsequent new layouts.
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