The semiconductor industry is growing at an annual rate of 6.9%, and the production of semiconductor devices is increasing accordingly. Currently, device manufacturing using Extreme Ultraviolet (EUV), referred to as 2 nm technology, has begun for AI and mobile phone devices. On the other hand, the production of devices using >90nm technology, known as mainstream, for the automobile industry and sensing devices, including power, analog, and discrete, is also increasing, leading to an increase in the production of photomasks. However, the reality is that the production of photomasks for the relevant technology is using outdated equipment, and there is a need for equipment with high productivity. In this study, we investigate how e-beam masks for devices used in the mainstream technology compares to masks manufactured with current high-productivity DUV laser equipment and will focus on the following aspects and provide a comprehensive report. Comparison with manufactured masks based on current technologies in terms of CDU, Registration, resolution, printability and so on.
EUV Lithography is an important technology that drives semiconductor device miniaturization. It is currently undergoing high volume manufacturing (HVM) of 3 nm logic node and development of 2 nm node by leading-edge semiconductor manufacturers. EUV mask technology is becoming increasingly important factor for EUV lithography. Mask resolution requirement is under 25nm for 2nm node Technology node. DNP has developed the EUV mask process with using the low-sensitivity-high-resolution resist and multi beam mask writer (MBMW) and This process shows promising capability on the resolution for 2nm Logic technology. For A14 Technology need more high resolution mask, In this paper, we present a comprehensive study on mask processes that possess a resolution of 20nm or below and techniques aimed at enhancing lithography contrast.
In semiconductor manufacturing for the 3nm node, 2nm node and beyond generations, Extreme ultraviolet lithography (EUVL) is an essential technology, and within that, photomask technology plays an important role. Currently, photomasks for EUVL are manufactured with a multi beam mask writer (MBMW) that uses over 200,000 electron beams to achieve high efficiency and high precision. However, it is said that the chemical amplification resist for EB lithography has already reached its limit, and forming a 10nm pattern on a mask is extremely difficult. Last year, We reported mask development using Ultra High Resolution CAR resists. In this report, we present the latest mask development status using chemical amplification resists and alternative resists to achieve even higher resolution.
Today, the semiconductor industry is booming, because data centers, state-of-the-art devices, power semiconductors, etc. have high demand. In particular, EUV is leading the industry as a novel technology for advanced lithography. On the other hand, mature product lines are also supporting the overall semiconductor industry as a whole. Photomasks have become a very important key parameter for the semiconductor industry. The manufacture of photomasks with stable quality and on-time delivery is essential for stable chip production, but it is very challenging to identify manufacturing problems because of the wide variety of photomasks and patterns. In this study, we established a methodology to analyze the data of various equipment, processes, and materials in photomask manufacturing, and obtained various improvement results using Digital Transformation.
The 1Xnm technology node lithography is using SMO-ILT, NTD or more complex pattern. Therefore in mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask feature. One key Technology of mask manufacture is defect verification to use aerial image simulator or other printability simulation. AIMS™ Technology is excellent correlation for the wafer and standards tool for defect verification however it is difficult for verification over hundred numbers or more.
We reported capability of defect verification based on lithography simulation with a SEM system that architecture and software is excellent correlation for simple line and space.[1]
In this paper, we use a SEM system for the next generation combined with a lithography simulation tool for SMO-ILT, NTD and other complex pattern lithography. Furthermore we will use three dimension (3D) lithography simulation based on Multi Vision Metrology SEM system. Finally, we will confirm the performance of the 2D and 3D lithography simulation based on SEM system for a photomask verification.
Even small defects on the main patterns can create killer defects on the wafer, whereas the same defect on or near the decorative patterns may be completely benign to the wafer functionality. This ambiguity often causes operators and engineers to put a mask "on hold" to be analyzed by an AIMS™ tool which slows the manufacturing time and increases mask cost. In order to streamline the process, mask shops need a reliable way to quickly identify the wafer impact of defects during mask inspection review reducing the number of defects requiring AIMS™ analysis.
Source Mask Optimization (SMO) techniques are now common on sub 20nm node critical reticle patterns These techniques create complex reticle patterns which often makes it difficult for inspection tool operators to identify the desired wafer pattern from the surrounding nonprinting patterns in advanced masks such as SMO, Inverse Lithography Technology (ILT), Negative Tone Development (NTD).
In this study, we have tested a system that generates aerial simulation images directly from the inspection tool images. The resulting defect dispositions from a program defect test mask along with numerous production mask defects have been compared to the dispositions attained from AIMS™ analysis. The results of our comparisons are presented, as well as the impact to mask shop productivity.
In a Photomask manufacturing process, mask defect inspection is an increasingly important topic for 193nm optical lithography. Further extension of 193nm optical lithography to the next technology nodes, staying at a maximum numerical aperture (NA) of 1.35, pushes lithography to its utmost limits. This extension from technologies like ILT and SMO requires more complex mask patterns. In mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask features. One of the solutions is lithography simulation like AIMS. An issue with AIMS, however, is the low throughput of measurement, analysis etc.
The retardation of the development of NGL techniques causes the extension of ArF immersion lithography for 1x-nm node. We have been researching the new phase shift mask's (PSM) material for the next generation ArF lithography. In this reports, we developed the low-k, high transmission PSM and evaluate it. The developed new PSM shows good lithographic performance in wafer and high ArF excimer laser durability. The mask processability were confirmed such as the CD performance, the cross section image, the inspection sensitivity and repair accuracy.
We have developed a new focused ion beam (FIB) technology using a gas field ion source (GFIS) for mask repair.
Meanwhile, since current high-end photomasks do not have high durability in exposure nor cleaning, some new
photomask materials are proposed. In 2012, we reported that our GFIS system had repaired a representative new material
“A6L2”. It is currently expected to extend the application range of GFIS technology for various new materials and
various defect shapes. In this study, we repaired a single bridge, a triple bridge and a missing hole on a phase shift mask
(PSM) of “A6L2”, and also repaired single bridges on a binary mask of molybdenum silicide (MoSi) material “W4G”
and a PSM of high transmittance material “SDC1”. The etching selectivity between those new materials and quartz were
over 4:1. There were no significant differences of pattern shapes on scanning electron microscopy (SEM) images
between repair and non-repair regions. All the critical dimensions (CD) at repair regions were less than +/-3% of those at
normal ones on an aerial image metrology system (AIMS). Those results demonstrated that GFIS technology is a reliable
solution of repairing new material photomasks that are candidates for 1X nm generation.
193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Multi-patterning of an increasing number of critical layers puts extreme pressure on wafer intra-field overlay, to which mask registration error is a major contributor [1]. The International Technology Roadmap for Semiconductors (ITRS [2]) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Full characterization of mask registration errors in the active area of the die will become mandatory. It is well-known that differences in pattern density and asymmetries in the immediate neighborhood of a feature give rise to apparent shifts in position when measured by optical metrology systems, so-called optical proximity effects. These effects can easily be similar in magnitude to real mask placement errors, and uncorrected can result in mis-qualification of the mask. Metrology results from KLA-Tencor’s next generation mask metrology system are reported, applying a model-based algorithm [3] which includes corrections for proximity errors. The proximity corrected, model-based measurements are compared to standard measurements and a methodology presented that verifies the correction performance of the new algorithm.
Optical lithography stays at 193nm with a numerical aperture of 1.35 for several more years before moving to
EUV lithography. Utilization of 193nm lithography for 45nm and beyond forces the mask shop to produce
complex mask designs and tighter lithography specifications which in turn make process control more
important than ever. High yield with regards to chip production requires accurate process control.
Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and
reliable functionality of any integrated circuit. There are different contributors which impact the total wafer
CDU, mask CD uniformity, resist process, scanner and lens fingerprint, wafer topography, etc.
In this paper, the wafer level CD metrology tool WLCD of Carl Zeiss SMS is utilized for CDU measurements
in conjunction with the CDC tool from Carl Zeiss SMS which provides CD uniformity correction. The
WLCD measures CD based on proven aerial imaging technology. The CDC utilizes an ultrafast femto-second
laser to write intra-volume shading elements (Shade-In ElementsTM) inside the bulk material of the mask. By
adjusting the density of the shading elements, the light transmission through the mask is locally changed in a
manner that improves wafer CDU when the corrected mask is printed.
The objective of this study is to evaluate the usage of these two tools in a closed loop process to optimize
CDU of the mask before leaving the mask shop and to ensure improved intra-field CDU at wafer level.
Mainly we present the method of operation and results for logic pattering by using these two tools.
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