EUV lithography (EUVL) is the most promising solution for 16nm HP node semiconductor device manufacturing and
beyond. The fabrication of defect free EUV mask is one of the most challenging roadblocks to insert EUVL into high
volume manufacturing (HVM). To fabricate and assure the defect free EUV masks, electron beam inspection (EBI) tool
will be likely the necessary tool since optical mask inspection systems using 193nm and 199nm light are reaching a
practical resolution limit around 16nm HP node EUV mask. For production use of EBI, several challenges and potential
issues are expected. Firstly, required defect detection sensitivity is quite high. According to ITRS roadmap updated in
2011, the smallest defect size needed to detect is about 18nm for 15nm NAND Flash HP node EUV mask. Secondly,
small pixel size is likely required to obtain the high sensitivity. Thus, it might damage Ru capped Mo/Si multilayer due
to accumulated high density electron beam bombardments. It also has potential of elevation of nuisance defects and
reduction of throughput. These challenges must be solved before inserting EBI system into EUV mask HVM line.
In this paper, we share our initial inspection results for 16nm HP node EUV mask (64nm HP absorber pattern on the
EUV mask) using an EBI system eXplore® 5400 developed by Hermes Microvision, Inc. (HMI). In particularly, defect
detection sensitivity, inspectability and damage to EUV mask were assessed. As conclusions, we found that the EBI
system has capability to capture 16nm defects on 64nm absorber pattern EUV mask, satisfying the sensitivity
requirement of 15nm NAND Flash HP node EUV mask. Furthermore, we confirmed there is no significant damage to
susceptible Ru capped Mo/Si multilayer. We also identified that low throughput and high nuisance defect rate are critical
challenges needed to address for the 16nm HP node EUV mask inspection. The high nuisance defect rate could be
generated by poor LWR and stitching errors during EB writing of 64nm HP resist pattern. This result suggests we need
further improvements not only in the EBI inspection system but also the patterning processes for 16nm HP node EUV
masks.
The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops
face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable
writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data
volumes continuously grows.
Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the
mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible
contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity
effect correction is able to meet the dual challenge of the new generation of masks.
Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and
geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between
accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the
Inscale software package from Aselta Nanographics.
We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time
has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly
compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect
correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy
and e-beam write time.
EUVL pilot line will be launched in 2012 with several pre-production tools installed in world wide. Since there
will be still the productivity issue on the exposure tool, certain demand of EUV masks may be required in 2012. In this
presentation, the status of EUV mask readiness, such as pattern quality, related infrastructures, and mask handling flow
etc., will be discussed.
Fabrication of defect free EUV masks including their inspection is the most critical challenge for implementing EUV
lithography into semiconductor high volume manufacturing (HVM) beyond 22nm half-pitch (HP) node. The contact to
bit-line (CB) layers of NAND flash devices are the most likely the first lithography layers that EUV will be employed for
manufacturing due to the aggressive scaling and the difficulty for making the pattern with the current ArF lithography.
To assure the defect free EUV mask, we have evaluated electron beam inspection (EBI) system eXplore™ 5200
developed by Hermes Microvision, Inc. (HMI) [1]. As one knows, the main issue of EBI system is the low throughput.
To solve this challenge, a function called Lightning Scan™ mode has been recently developed and installed in the system,
which allows the system to only inspect the pattern areas while ignoring blanket areas, thus dramatically reduced the
overhead time and enable us to inspect CB layers of NAND Flash device with much higher throughput.
In this present work, we compared the Lightning scan mode with Normal scan mode on sensitivity and throughput. We
found out the Lightning scan mode can improve throughput by a factor of 10 without any sacrifices of sensitivity.
Furthermore, using the Lightning scan mode, we demonstrated the possibility to fabricate the defect free EUV masks
with moderate inspection time.
Semiconductor lithography candidates toward 2xnm node and beyond include wide variety of options, such as
extension of 193i, EUVL, NIL, and ML2. Most of those candidates, except ML2, need critical mask feature to realize
effective high volume manufacturing. In this presentation, EUVL mask technology update and future issues will be
presented.
Fabrication of defect free EUV mask is one of the most critical roadblocks for implementing EUV lithography into
semiconductor high volume manufacturing for 22nm half-pitch (HP) node and beyond. At the same time, development
of quality assurance process for the defect free EUV mask is also another critical challenge we need to address before the
mass production. Inspection tools act important role in quality assurance process to ensure the defect free EUV mask. We
are currently evaluating two types of inspection system: optical inspection (OPI) system and electron beam inspection
(EBI) system [1, 2]. While OPI system is sophisticated technology and has an advantage in throughput, EBI system is
superior in sensitivity and extendability to even small pattern.
We evaluated sensitivity of EBI system and found it could detect 25 nm defects on 88nm L/S pattern which is as small
as target defect size for 23 nm Flash HP pattern in 2013 in 2009 ITRS lithography roadmap [2, 3]. EBI system is
effective inspection tool even at this moment to detect such small defects on 88nm HP pattern, though there are still
some challenges such as the slow throughput and the reliability. Therefore, EBI system can be used as bridge tool to
compensate insufficient sensitivity of current inspection tools and improve EUV mask fabrication process to achieve the
defect free EUV mask. In this paper, we will present the results of native pattern defects founded on large field 88nm HP
pattern using advance EBI system. We will also classify those defects and propose some ideas to mitigate them and
realize the defect free EUV mask, demonstrating the capability of EBI as bridge tool.
Achieving the specifications of line width roughness (LWR), sensitivity and resolution of wafer resist is one of the top
challenges of bringing extreme ultraviolet lithography (EUVL) into high volume manufacturing. At the same time,
EUV mask LWR is set on very ambitious target value from ITRS [1] because mask LWR would contribute to wafer
resist LWR more strongly than that of ArF lithography due to dramatic decrease of wavelength.
Mutual relation between mask and wafer resist LWR has been discussed [2] [3] but not frequently, so standardization of
mask LWR measurement is not fixed. SEM image analysis is common to measure mask LWR but the value depends on
measurement parameters such as segment length of pattern edge.
In this paper, optimum measurement conditions with SEM will be investigated and discussed using SEM images of
actual mask and aerial simulation. And also we will report development status of actual mask LWR.
The load of VSB-EB mask writers has significantly increased since particularly RET/OPC and CMP dummy pattern
generation technologies were widely adopted into designs at advanced nodes, with the result that the volume of mask
data patterns was increased exponentially. In order to reduce the load of VSB mask writer, we've focused on CMP
dummy patterns and developed a method of reducing CMP dummy pattern, which can smartly write CMP dummy
patterns without not only deteriorating the CMP effects by them and also increasing the total number of the mask
writer's shot count. To that end, we are aiming to establish a
VSB-mask-writer-friendly CMP dummy pattern generation
flow with CMP simulator developers by providing a mask writer parameter for them.
This paper shows the first experimental results of our mask writer's load reduction work.
When a thinner absorber mask is practically applied to the extreme ultraviolet lithography for ultra large scale integration chip production, it is inevitable to introduce an extreme ultraviolet (EUV) light shield area to suppress leakage of the EUV light from adjacent exposure shots. We believe that a light-shield border of the multilayer etching type is a promising structure in terms of mask process flexibility for higher mask critical dimension accuracy. We evaluate the etching impact of the absorber and multilayer on the mask flatness and image placement change through the mask process of a thin absorber mask with a light-shield border of the multilayer etching type structure. We clarify the relation between mask flatness and mask image placement shift.
Readiness of defect-free mask is one of the biggest challenges to insert extreme ultraviolet (EUV) lithography into
semiconductor high volume manufacturing for 22nm half pitch (HP) node and beyond. According to ITRS roadmap
updated in 2008, minimum size of defect needed to be removed is 25nm for 22nm HP node in 2013 [1]. It is necessary,
therefore, to develop EUV mask pattern inspection tool being capable of detecting 25nm defect. Electron beam
inspection (EBI) is one of promising tools which will be able to meet such a tight defect requirement.
In this paper, we evaluated defect detection sensitivity of electron beam inspection (EBI) system developed by
Hermes Microvision, Inc. (HMI) using 88nm half-pitch (HP) line-and-space (L/S) pattern and 128nm HP contact-hole
(C/H) pattern EUV mask. We found the EBI system can detect 25nm defects. We, furthermore, fabricated 4 types of
EUV mask structures: 1) w/ anti-reflective (AR) layer and w/ buffer layer, 2) w/ AR layer and w/o buffer layer, 3) w/o
AR layer and w/ buffer layer, 4) w/o AR layer and w/o buffer layer. And the sensitivity and inspectability for the EBI
were compared. It was observed that w/o AR layer structure introduce higher image contrast and lead to better
inspectability, although there is no significant different in sensitivity.
When thinner absorber mask is practically applied to the EUVL for the ULSI chip production, it is inevitable to
introduce EUV light shield area in order to suppress leakage of the EUV light from adjacent exposure shots. We believe
that light-shield border of multilayer etching type is promising structure in terms of mask process flexibility for higher
mask CD accuracy
In this paper, we evaluate etching impact of absorber and multilayer on mask flatness and image placement change
through mask process of thin absorber mask with light-shield border of multilayer etching type structure. And then, we
clarify the relation between mask flatness and mask image placement shift.
Extreme Ultra Violet Lithography (EUVL) is the most leading next generation lithographic
technology post ArF immersion lithography. The Structure of EUV mask differ from traditional
photomask., especially backside coating.
E-chuck is employed to fix the EUV mask on the scanner. Therefore a conductive film on
backside of the EUV mask blank is needed. We investigated what have an influence on mask
manufacturing process caused by the backside coating differed from a traditional photomask.
From our experiment, at the mask fabrication process, especially RIE process to etch Ta
absorber, the CD variation is occurred by electric conduction between the backside conductive
coating and the absorber on the Mo/Si multi-layer.
As a result, the EUV mask blank without electric conduction between the backside conductive
coating and the absorber on the Mo/Si multilayer is necessary.
The effect of mask structure with light shield area on the printability in EUV lithography was studied. When very
thin absorber on EUVL mask is used for ULSI application, it then becomes necessary to create EUV light shield area
on the mask in order to suppress possible leakage of EUV light from neighboring exposure shots. We proposed and
fabricated two types of masks with very thin absorber and light shield area structure. For both types of masks we
demonstrated high shield performances at light shield areas by employing a Small Field Exposure Tool (SFET).
In EUV lithography, particle-free handling is one of the critical issues because a pellicle is impractical due to its high
absorption. To investigate this subject, we have developed a mask protection engineering tool that allows various types
of tests to be carried out during the transfer of a mask or blank in air and in vacuum. We measured the number of particle
adders during the transfer of a mask blank in a dual-pod carrier and in an RSP200 carrier. We found that the number of
particle adders (>=46 nm PSL) to a mask blank in a dual pod is less than 0.01 over the whole process from taking the
blank out of the load port in air to putting it in the electrostatic chuck chamber in vacuum. Through various experiments,
the number of particle adders during any process using a dual pod was found to be very few and very stable. In contrast,
for a naked mask, many particle adders were found in large variations. Below one particle were added in over 80% of
experiments on a dual pod and in about 20% of experiments on a naked mask. Based on the test results, we can conclude
that the use of dual pod is an excellent particle-free transfer technique.
"Reticle protection during storage, handling and use" is one of the critical issues of EUV lithography because no
practical pellicle has been found for EUV reticles as yet. The front surface of an EUV reticle has to be protected from
particles larger than 20-30 nm to maintain the image quality on the wafer plane, and the backside also has to be protected
to maintain the flatness of the reticle chucked on an electrostatic chuck (ESC). In this paper, we are focusing on particles
on the backside of the reticle. If a particle lies between the reticle and the chuck, it has a strong impact on the flatness of
the reticle, and the wafer overlay is degraded by out-of-plane distortion (OPD) and in-plane distortion (IPD) due to the
particle1-5. From this point of view, we need to know the maximum permissible size of particles on the backside of the
reticle. MIRAI-Selete introduced an experimental setup that can measure the flatness of the chucked reticle in a vacuum.
An electrostatic chuck is installed in the vacuum chamber of Mask Protection Engineering Tool (MPE Tool)6, a reticle is
automatically carried from a reticle pod to the chuck in the tool. The flatness of the reticle can be measured by an
interferometer through a viewport underneath the chamber. We can measure the reticle flatness with 3-nm@rms
reproducibility using this setup. We report results of experimental evaluation about the relationship between the reticle
OPD, the size of particle and the chucking force of ESC.
Nanoimprint lithography is a candidate for lithography for the hp32nm and hp22nm nodes. Molds or templates
for it are being developed on the basis of the process of making phase-shift photomasks. The combination of a 50
kV-VSB (variable shaped beam) EB writer and a chemically amplified resist (CAR) does not have a resolution sufficient
for 1X patterning. On the other hand, a combination of a 100 kV-SB (spot beam) EB writer and a non-CAR satisfies the
resolution requirement, but this combination leads to an extremely low throughput due to low resist sensitivity.
To increase the throughput, we have examined double patterning and double exposure with hybrid use of two
different types of writers, a 50 kV-VSB writer, JBX-9000MV, for delineating fine features and a 100 kV-SB writer,
JBX-9300FS, for delineating rough features. Overlay accuracy is a key item in such hybrid writing. The results of an
overlay accuracy evaluation together with a throughput improvement will be reported in this paper. An estimation of the
time for writing a gate layer has given a good example; the writing time for hybrid writing is reduced to about half of the
time for 100kV-SB writing. The overlay accuracy for double patterning is found to be 20nm (3σ). However, we are
confident that we will be able obtain an overlay accuracy of 10nm (3σ) by improving the image placement accuracy of
the JBX-9300FS. An example of double exposure is also shown.
We have developed a mask protection engineering tool (MPE Tool) that simulates various types of tests during the
transfer of a mask or blank in air and in vacuum. We performed mask transfer experiments to investigate particle-free
mask handling techniques using the MPE and mask inspection tools. We measured the number of particles accumulated
during the transfer of the mask blanks. Less than 0.3 particles were added over a path from a load port (in air) to an ESC
chamber (in vacuum) and more than half the particles accumulated appeared during the pumping down and purging steps
in the load-lock chamber. Consequently, we consider that pumping down and purging are the most important steps for
particle-free mask handling.
We, MIRAI-Selete, started a new EUV mask program in April, 2006. Development of EUV mask handling technology is
one of the key areas of the program. We plan to develop mask handling technology and to evaluate EUV mask carriers
using Lasertec M3350, a particle inspection tool with the defect sensitivity less than 50nm PSL, and Mask Protection
Engineering Tool (named "MPE Tool"). M3350 is a newly developed tool based on a conventional M1350 for EUV
blanks inspection. Since our M3350 has a blank flipping mechanism in it, we can inspect the front and the back surface
of the blank automatically. We plan to use the M3350 for evaluating particle adders during mask shipping, storage and
handling. MPE Tool is a special tool exclusively developed for demonstration of pellicleless mask handling. It can
handle a mask within a protective enclosure, which Canon and Nikon have been jointly proposing1, and also, can be
modified to handle other type of carrier as the need arises.
Three stencil masks with simple die layouts on 24 mm x 24 mm Si membranes are made to compare simulation and experiment on image placement (IP). A pseudo finite element (FE) modeling is adopted. Displacements predicted by simulation are found to be smaller than experimental values, but both agree qualitatively. Four stencil masks with die layouts that model on ULSI hole layers in 30% opening ratio and pattern arrangement are successfully made. Displacements are reduced to 1/4 by adopting IP correction. The IP correction of EB data is found to be a useful method of reducing IP error.
EB lithography has a potential to successfully form hole patterns as small as 80 nm with a stencil mask. In a previous paper we proposed a technique using a HOLON dual-mode critical dimension (CD) SEM ESPA-75S in the transmission mode for CD measurement of line-and-space patterns on a stencil mask. In this paper we extend our effort of developing a CD measurement technique to contact hole features and determine it in comparison of measured values between features on mask and those printed on wafer. We have evaluated the width method and the area methods using designed 80-500 nm wide contact hole patterns on a large area membrane mask and their resist images on wafer printed by a LEEPL3000. We find that 1) the width method and the area methods show an excellent mask-wafer correlation for holes over 110 nm, and 2) the area methods show a better mask-wafer correlation than the width method does for holes below 110 nm. We conclude that the area calculated from the transmission SEM image is more suitable in defining the hole dimensions than the width for contact holes on a stencil mask.
Electron beam projection lithography (EPL) has been developed for application to 65 nm node devices and beyond. 200-mm EPL masks have also been developed keeping pace with the exposure tool. Image placement (IP) accuracy is a necessary quality assurance item to bring masks into production. A suspension type electrostatic chuck designed for EPL mask measurement for an IP metrology tool Leica LMS IPRO was prepared for measurement of local IP errors, defined for each subfiled. The chuck holds the mask on its membrane-side surface right side up. Three 200-mm stencil masks with tensile membrane stresses of 8, 18, and 43 MPa were fabricated. The IP error is found to increase as the stress increases. Marks in the area of a high pattern density with a void fraction of 0.2 moved toward the area of a low pattern density with a void fraction of 0.016. The IP errors did not strongly depend on the kinds of dummy patterns (either hole or L&S) having the same void fraction of 0.25 and macroscopic uniformity. If the stress is less than 10 MPa, the IP error (3 sigma) is less than 10 nm, satisfying the EPL mask requirement. Local CD accuracy was also evaluated for a mask with a membrane stress of 8 MPa.
Higher resolution and accuracy are required in e-beam lithography for reticle fabrication for coping with further advances in optical lithography. The trend is to use high acceleration voltage (50 kV) e-beam to improve spatial resolution. However, in the case of high acceleration e-beam writing, a drastic critical dimension (CD) change is caused by a strong proximity effect and a large resist heating effect. The proximity effect is caused by the increase in the back- scattering radius. The back-scattering radius was estimated by two independent observations of the CD variation of a monitor and the thickness variation of a partially developed resist. It is found to be ca. 15 nm. Using the shot time modulation as a proximity correction reduced the proximity effect to a small level: CD error due to the pattern density change remained within 10 nm. On the other hand, the resist heating effect is caused by the change in resist dissolution speed by the temperature rise of the resist. In reducing this effect, multi-pass writing is found to be effective. The range of the CD error of 2 micrometer lines-and-spaces in the writing field has been reduced from 22 nm to 6 nm by changing the writing from one pass to four passes for a conventional resist. Moreover, when a chemically amplified resist (CAR) is exposed through one-pass writing, the range of the CD error is found to be 8 nm. Therefore, the use of the CAR is effective in reducing the resist heating effect. Simulation software ProBEAM/3D and TEMPTATION were used to obtain three- dimensional resist profile and the transient temperature rise of the resist, respectively. Both provided results that agreed well with those by experiment.
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