With the continuous shrinking of semiconductor device nodes, the reduction of on-product overlay (OPO) becomes extremely critical for high-yield IC (Integrated Circuit) manufacturing. This requires accurate overlay (OVL) process control which can be better achieved by using an optimized OVL target design and a more advanced metrology platform. The novel rAIM® imaging-based-overlay (IBO) target, which has a grating-over-grating structure with significantly smaller pitch sizes as compared to the standard advanced-imaging-metrology (AIM®) target, can improve OVL measurement accuracy by adopting a more device-compatible design with high Moiré sensitivity. This paper demonstrates the advantages of rAIM targets by comparing and quantifying their performance to standard AIM targets through key parameters including raw OVL, residuals, precision, and total measurement uncertainty (TMU). We also present the performance of rAIM targets on different OVL metrology platforms. We conclude that with an optimized target design and an advanced OVL measurement platform, rAIM targets can be an ideal overlay metrology solution for advanced dynamic random-access memory (DRAM) devices.
In modern DRAM processes, there are some critical layers that are particularly challenging for overlay (OVL) control. The conventional method of metrology target design for these challenging layers is to verify target performance using simulation based on the specific, final device process. After full simulations, target measurability issues can be encountered where the limited, available solutions (open hard mask, create topography, etc.) are costly and high risk. However, in DRAM new product R&D, there is always some tolerance for process tuning. The use of virtual Archer™ OVL measurements in metrology target design (MTD) can simulate metrology performance for these potential process splits, helping to find a good balance between process options and metrology performance. A significant improvement in target contrast for imaging-based overlay (IBO) is demonstrated by simulation on one of these challenging layers after process optimization as compared to the baseline (BSL) process. In this paper we will present the virtual MTD detailed flow and design considerations to achieve an optimized process and target design. The contrast of a key performance indicator (KPI) is improved by more than 30%, enabling OVL measurability of the challenging layer in new processes.
As design nodes of advanced semiconductor chips shrink, reduction in on-product overlay (OPO) budget becomes more critical to achieving higher yield. Imaging-based overlay (IBO) targets usually consist of periodic patterns where their pitches are resolvable with visible light microscopy. The difference between the feature dimensions of the device and the optical target is growing as device design nodes shrink. To make the optical target emulate the device as much as possible, the target’s feature periodicity is reduced. Using this approach, the process impact on the device is simulated on the overlay target which enables a more accurate measurement on grid (target) in terms of OPO matching. To further optimize IBO performance, a new moiré effect based robust Advanced Imaging Mode (rAIM™) target design was developed. This rAIM IBO target is implemented using significantly smaller pitches compared to the standard AIM® target, resulting in a more device-like target design. In this paper we investigate the benefits of the optical improvement, manifested as the target gain, and the process compatibility benefits to improve the target accuracy, robustness, and measurability to meet overlay (OVL) basic performance requirements, such as total measurement uncertainty (TMU).
Reduction in on product overlay (OPO) is a key component for high-end, high yield integrated circuit manufacturing. Due to the continually shrinking dimensions of the IC device elements it has become near-impossible to measure overlay on the device itself, driving the need to perform overlay measurements on dedicated overlay targets. In order to enable accurate measurement on grid (target) in terms of OPO matching, the overlay mark must be as similar as possible to the device in order to mimic the process impact on the device. Imaging-based optical overlay (IBO) provides the best accuracy and robustness for overlay metrology measurements for many process layers. To further optimize IBO performance, a new robust AIM (rAIM™) IBO target design was developed, using the Moiré effect. rAIM is implemented using significantly smaller pitches compared with the standard AIM® target, hence providing a more device-like target design. This new target design has the potential to improve target accuracy and robustness, to improve measurability, and to meet overlay basic performance requirements, such as total measurement uncertainty (TMU).
In recent years, simulation-based analysis has become an integral phase in metrology targets design process, performances optimization wise to support on product overlay (OPO) reduction, accuracy and robustness to process variation. Moreover, a simulated unit (stack) represented by its optical and geometrical properties can be used as a mathematicalphysical object for obtaining a deeper understanding of the issues faced while an actual measurement performed. Location based stack calibration allows for both, symmetrical and asymmetrical process variation, a noticeable wafer signature to be attained. Using this information, one can analyze the target-design process-compatibility and asymmetry stability. Furthermore, simulated data can be used, combined with measured data, to establish a more exhaustive perceiving of the process characteristics and risks, hence maxims the measurement performances and stability of the process and target behavior. Likewise, simulation tools can equip integration teams with a more holistic apprehension and quantified data, prior or along real time measurements. In the paper we will cover the simulation theory, use-cases and results.
On product overlay (OPO) challenges continue to be yield limiters for most advanced technology nodes, requiring new and innovative metrology solutions. In this paper we will cover an approach to boost accuracy and robustness to process variation in imaging-based overlay (IBO) metrology by leveraging optimized measurement conditions per alignment layer. Results apply to both DUV and EUV lithography for advanced Logic, DRAM, 3D NAND and emerging memory devices. Such an approach fuses multi-signal information including Color Per Layer (CPL) and focus per layer. This approach with supporting algorithms strives to identify and address sources of measurement inaccuracy to enable tight OPO, improve accuracy stability and reduce overlay (OVL) residual error within the wafer and across lots. In this paper, we will present a theoretical overview, supporting simulations and measured data for multiple technology segments. Lastly, a discussion about next steps and future development will take place.
For today’s advanced processes, in order to achieve higher optical lithography resolution, some of the layers require extreme dipole illumination conditions. One example is the modern DRAM process, where numerous critical layers are patterned with extreme dipole scanner illumination. Conventional (both imaging-based and diffraction-based) overlay marks on such layers typically use horizontal or vertical lines that suffer from insufficient accuracy in overlay device tracking. The new Diagonal AIM (DAIM™) overlay mark mimics the actual device through the usage of tilted structures. Significant improvement in device overlay tracking was demonstrated using the DAIM overlay mark.
A fast model is developed for the simulation of the mask diffraction spectrum in extreme ultraviolet lithography. It combines a modified thin mask model and an equivalent layer method and provides an analytical expression of the diffraction spectrum of the mask. Based on this model, we perform a theoretical analysis of the mask shadowing effect. Mathematical expressions for the best mask (object space) focus position and for the required correction of the mask pattern size are derived. When the mask focus is positioned in the equivalent plane of the multilayer, the amount of pattern shift is reduced. When the mask pattern size is corrected using the derived formula, taking a space pattern with a target critical dimension (CD) of 22 nm as an example, the imaging CD bias between different oriented features is below 0.3 nm.
A fast rigorous model is developed for the simulation of mask diffraction spectrum in EUV lithography. It combines a modified thin mask model and an equivalent layer method and provides an analytical expression of the diffraction spectrum of mask. Based on this model, we propose a theoretical analysis of the mask shadowing effect. Mathematical expressions for the best mask (object space) focus position and for the required correction of mask pattern size are derived. When the mask focus is positioned in the equivalent plane of the multilayer, the amount of pattern shift is reduced. When the mask pattern size is corrected using the derived formula, taking a space pattern with the target CD of 22 nm as an example, the imaging CD bias between different oriented features is below 0.3 nm.
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