Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, ∼0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps decoding throughput was achieved, better than the theoretical key rate of prototype of CVQKD.
The Continuous-variable quantum key distribution (CVQKD) technique is one of the practical uses of quantum information technology. CVQKD system is implemented based on existing optical networks and standard telecommunication technologies. CVQKD can be put into use of the information transmission in city-based areas, within the extent of absolute security and without any restrictions of security. To reduce the experimental system to a commercial prototype, a data acquisition (DAQ) card can be used to replace the DAQ equipment in the laboratory. It can save the cost of the system experiment and commercial application. In this paper, through the high-speed DAQ card, we implement the collection and uploading of the electrical signal, when the light passes through the continuous optical coherent state detector. The whole experiment test system consists of a field-programmable gate array (FPGA), an analog-to-digital converter (ADC) chip, and optical components. This paper provides a method of gain adjustment of the balanced homodyne detector and a way to test the π phase voltage of the optical modulator. The results show that the DAQ card can be used in the development of the CVQKD prototype.
The continuous-variable quantum key distribution experimental system requires the randomness and speed of a Gaussian modulator. We present the hardware design for a Gaussian random number (GRN) generator based on the Box–Muller method, which can be implemented on a field-programmable gate array (FPGA). An external high-speed true random number generator application-specific integrated circuit (ASIC) is used to this end. The ASIC operates faster and more independently compared with other Gaussian algorithms based on a linear feedback shift register. The trigonometric and logarithmic functions are calculated using the nonuniform piecewise linear approximation. The calculation of the Gaussian random modulus and phase value is realized using this hardware. Compared with an arbitrary waveform generator, the GRN can be uploaded to a computer to estimate the security key rate. Furthermore, the GRN generator accurately provides a Gaussian probability density function that passes the Jarque–Bera inspection and Lilliefors tests. The proposed FPGA-based system is demonstrated to convert eight-channel 320-Mbps uniform random numbers to 40-MHz 16-bit GRN in real time. Finally, the control of the optical module and Gaussian modulation is realized via the FPGA-based outputs of four dual-channel, 16-bit, 1-giga samples per second digital-to-analog converters.
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